CS4216 datasheet(48/58 Pages) CIRRUS

48 / 58 page

CONTROL PORT HEADER

The Control Port Header J14 contains the control

port pins, available only in SM4, and the PDN

and RESET pins.

Serial mode 4, SM4, splits the serial data to the

codec into two separate serial ports, the audio

port and the control port. The control port pins

are available on this header. Since CDOUT is

buffered and always driven, it cannot be used on

a shared serial port. Although the INT pin on the

codec is open drain, the default factory configu-

ration for the eval board is an on-board pull-up

resistor and a buffer. Therefore, the INT header

pin cannot share an interrupt pin on a processor

since it is buffered and will always be driven. By

cutting a trace in the J18 jumper, the unbuffered

INT signal, labeled U, can be supplied to the

header. When using the control port, the LB

switch must be off or the control serial port will

be blocked.

PDN and RESET

PDN is buffered and controls the PDN pin on

the CS4216. PDN contains an on-board pull-up

resistor defining the default state as powered.

This pin only needs to be controlled when the

power down feature is used.

RESET is also buffered and controls the RESET

pin on the codec (see Figure 6). RESET has a

pull-up resistor on the board defining the default

state as not reset or active. This pin only needs

to be controlled when the reset feature on the

codec is needed. Since the codec requires a reset

at power up, a power-up reset circuit is included

on the board. A reset switch is also included to

allow resetting the device without having to re-

move the power supply. The power-up reset plus

switch are logically ORed with the RESET pin

on header J14.

DIGITAL I/O HEADER

The Digital I/O Header, J13 shown in Figure 4,

contains the four digital inputs, DI1-DI4, and the

four digital outputs, DO1-DO4. Note that all

digital I/O except DI1 and DO1 are multifunc-

tion pins and may not be available in a particular

mode. Since DO1 is always a digital output, an

LED is connected to DO1 providing a visual in-

dication that software is writing this bit correctly.

When the LED is on, DO1 is high.

In SM1 and SM2 all four digital inputs and out-

puts are available. In SM3 master sub-modes,

only the first two inputs and outputs are func-

tional. In SM3 slave sub-modes, three inputs and

two outputs are functional. In SM4 only DO1

and DI1 are functional. See the CS4216/8 Data

Sheet for more details.

CLOCKS

The CDB4216/8 provides an on-board default

clock oscillator of 11.2896 MHz (see Figure 7).

This allows all 44.1 kHz and derivative sample

frequencies in SM3 Master sub-mode, SM3

Slave sub-mode, SM4, and the I

2S mode. The

CS4218 SM3-MM and SM3-MS modes require

a master clock of 16xFsmax. If using SM1, a

master clock with a frequency that is 512xFsmax

must be supplied. SM2 uses SCLK as the master

clock ant it must be 256xFsmax. A CLKIN BNC

allows the eval board to be driven from an exter-

RESET

U11

74HC132

47.5k

100

SW1A

47.5k

1N4148

CS4216

RESET

+ C1

1 uF

Figure 6. Reset Circuit

CDB4216

DS83DB4

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