CS4216 datasheet(44/58 Pages) CIRRUS

44 / 58 page

setting the MF8 pin high. Since the part is in

slave mode, the sampling rate must be set by the

ratio between CLKIN and SCLK.

Assuming

that CLKIN has a frequency of 11.2896MHz,

this ratio must be eight to give a sampling rate of

22.05kHz (refer to the CS4216 data sheet). In

all slave modes, SSYNC and SCLK must be

synchronous to the master clock.

LOOPBACK MODE

The CDB4216/8 may be configured in a simple

loop back mode that only requires a power

source to operate. No controller of any type is

necessary. This mode allows a quick and simple

verification of codec operation by sampling the

LIN1 and RIN1 inputs, then looping the digital

data back to the LOUT and ROUT line outputs.

Set SPF2=SPF1=MA=1 and shunt SDOUT to

SDIN on stake header J15. This mode uses SM4

with all control settings set to zero, so no gain or

attenuation is available.

POWER SUPPLY CIRCUITRY

Figure 1 illustrates a portion of the CDB4216/8

schematic and includes the CS4216/8 along with

power supply decoupling and circuitry. The

evaluation board supports various power supply

arrangements. The factory configuration powers

the analog portion of the CS4216/8, along with

input buffers, from the VA binding post, which

needs a clean +5 Volts. The digital portions of

the CS4216/8 are factory configured to obtain

power through a 2

Ω resistor from the VA supply.

The digital buffers and PLDs obtain power from

the VD binding post, which also needs +5 Volts.

Although binding posts exist for both digital and

analog grounds, only one needs to be connected

if a single supply is used for both VA and VD.

Note that the CS4216/8 is entirely on the analog

ground plane, close to the ground plane split as

required by the CS4216/8 Data Sheets. Also note

that the two ground planes are connected near

the two ground binding posts.

Space for a ferrite bead, L1, is provided so that

the board may be modified to power the codec

from the digital supply. Selection of L1 will de-

pend on the noise characteristics of the digital

supply used.

ANALOG INPUTS

The analog inputs consist of a pair of line level

inputs and a pair of

1/4" mono jacks for two mi-

crophones. BNC-to-phono adapters are included

to allow testing of the line inputs using coax or

standard audio cables.

The line-level inputs are connected to the

CS4216/8’s LIN1 and RIN1 pins. As shown in

Figure 2, the line-level inputs go through a buff-

er set to a gain of 0.5 which allows input signals

of up to 2 VRMS. When placed in serial mode 4

with loop back, the LIN1 and RIN1 inputs are

used for analog inputs.

The microphone inputs are connected to the

CS4216/8’s LIN2 and RIN2 pins. The two mi-

crophone inputs are single-ended and are

designed to work with both condenser and dy-

namic microphones. The microphone input

buffer, shown in Figure 3, has a gain of 23 dB

thereby defining a full-scale input voltage to the

microphone jacks of 71 mVRMS. Another 22 dB

of programmable gain is available on the

CS4216/8 to amplify smaller microphone sig-

nals.

An analog patch area with analog power and

ground, included on the CDB4216/8, provides

space to develop other input buffer circuits.

Space for headers are included, J19 and J20, to

connect to the LIN2 and RIN2 inputs. To use

these headers, the microphone traces must be

cut.

ANALOG OUTPUTS

The CS4216/8 drives the line outputs into an R-

C filter and then to a pair of BNCs labeled

CDB4216

DS83DB4

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