CS4216 datasheet(41/58 Pages) CIRRUS

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either serial mode 3, SM3, or serial mode 4,

SM4. Serial modes 1 and 2, SM1 and SM2, are

primarily designed for ASICs and are less flex-

ible. SM1 and SM2 are not available on the

CS4218. The CS4218 has additional SM3 sub-

modes: Multiplier Master (SM3-MM) and

Multiplier Slave (SM3-MS).

These sub-modes

are identical to the SM3 Master and Slave sub-

modes except that the master clock, CLKIN,

must be 16xFsmax instead of 256xFsmax. The

CS4218 also provides a master I

2S mode. In

master sub-modes, the CS4216/8 output SSYNC

and SCLK. In slave sub-modes, SSYNC and

SCLK must be externally generated and must be

synchronous to CLKIN.

Bits per Frame Selection

The next decision is selecting the number of bits

per frame which defines how many codecs can

sit on the same serial bus. Each codec occupies a

sub-frame and 1 to 4 sub-frames make up a

frame. A sub-frame is 64 bits in SM1, SM2, and

SM3; and 32 bits in SM4. Table 2 lists the possi-

ble selections. If the evaluation board serial port

is shared with other devices, SDOUTUB must be

used instead of SDOUT since SDOUTUB,

driven directly from the chip, must only drive

the time slot assigned to it. See the Audio Port

Header section for more information.

Time Slot Selection

If the number of bits per frame selected allows

for more than one codec sub-frame, then the ac-

tual time slot or sub-frame used by the eval

board must be selected. This is done with the

TS2 and TS1 DIP switches. If the number of bits

per frame allows only one codec on the serial

bus, then TS2 and TS1 are ignored. Table 3 list

the decoding for TS2 and TS1. Time slot 1 is the

first sub-frame after SSYNC goes high, time

slot 2 is the next sub-frame, and so on.

Sample Frequency Selection - Master Mode

The last decision is selecting the sample fre-

quency in master sub-mode. If configured for

slave sub-mode, the sample frequency is the ratio

of S C LK t o C LKIN as des c ri bed i n t h e

CS4216/8 Data Sheets. In master modes, three

pins are used to select the sample frequency di-

vide. The DIP switches labeled DIV1, DIV2, and

DIV3 select the sample frequency and are

equivalent to F1, F2, and F3, respectively. The

actual F1-F3 pins on the CS4216/8 are different

between SM3 and SM4 as shown in Table 4 at

the end of the data sheets. Table 3 and Table 9 of

the CS4216 Data Sheet describe the sample fre-

quencies obtained using the on-board oscillator

of 11.2896 MHz. As an example, if all DIV

switches are off, the sample frequency is

44.1 kHz. With only DIV2 on, the sample fre-

quency is 22.05 kHz.

To obtain a sample

frequency of 44.1 kHz using the CDB4218, all

DIV switches should be set to zero and a

705.6 kHz clock should be connected to the

BNC jack (J2). The shunt on J1 should be set to

EXT.

BPF

SM1

SM3

SM4

SM2

256

128

256

128

256

256*

128

* SCLK is master clock.

Table 2. DIP Switch, Bits per Frame

TS2

TS1

Available Sub-frames

Table 3. DIP Switch, Time Slots

CDB4216

DS83DB4

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