CS4216 datasheet(25/58 Pages) CIRRUS

25 / 58 page

nously (every audio frame) with respect to the

interrupt occurrence.

The third section is only needed if sample fre-

quencies need to be changed. This section is

comprised of an HC574 octal latch that can be

replaced by general purpose port pins if avail-

able. This section controls the sample frequency

selection bits: MF6:F1, MF7:F2, MF8:F3 and

the RESET pin. The codec must be reset when

changing sample frequencies.

Power Supply and Grounding

The CS4216, along with associated analog cir-

cuitry, should be positioned in an isolated section

of the circuit board, and have its own, separate,

ground plane. On the CS4216, the analog and

digital grounds are internally connected; there-

fore, the AGND and DGND pins must be

externally connected with no impedance between

them. The best solution is to place the entire

chip on a solid ground plane as shown in Fig-

ure 18. Preferably, it should also have its own

power plane. The +5V supply must be connected

to the CS4216 via a ferrite bead, positioned

closer than 1" to the device. The VA supply can

be derived from VD, as shown in Figure 1. Al-

ternatively, a separate +5V analog supply may be

used for VA, in which case, the 2.0

Ω resistor

between VA and VD should be removed. A sin-

gle connection between the CS4216 ground

(analog ground) and the board digital ground

should be positioned as shown in Figure 18.

Figure 19 illustrates the optimum ground and de-

coupling layout for the CS4216 assuming a

surface-mount socket and leaded decoupling ca-

pacitors. Surface-mount sockets are useful since

the pad locations are identical to the chip pads;

therefore, assuming space for the socket is left

on the board, the socket can be optional for pro-

duction. Figure 19 depicts the top layer,

containing signal traces, and assumes the bottom

or inter-layer contains a fairly solid ground

plane. The important points are that there is solid

ground plane under the codec on the same layer

as the codec and it connects all ground pins with

thick traces providing the absolute lowest imped-

ance between ground pins. The decoupling

capacitors are placed as close as possible to the

device which, in this case, is the socket bound-

ary. The lowest value capacitor is placed closest

to the codec. Vias are placed near the AGND and

DGND pins, under the IC, and should attach to

the solid ground plane on another layer. The

negative side of the decoupling capacitors should

also attach to the same solid ground plane.

Traces and vias bringing power to the codec

should be large, which minimizes the impedance.

Although not shown in the figures, the trace lay-

ers (top layer in the figures) should have ground

plane fill in-between the traces to minimize cou-

pling into the analog section. See the CDB4216

evaluation board as an example.

If using all surface-mount components, the de-

coupling capacitors should be placed on the

same layer as the codec and in the positions

shown in Figure 20. The vias shown are assumed

to attach to the appropriate power and ground

layers. Traces and vias bringing power to the

codec should be as large as possible to minimize

the impedance.

If using a through-hole socket, effort should be

made to find a socket with minimum height,

CS4216

DS83F2

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