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AS3658 датащи(PDF) 37 Page - ams AG

номер детали AS3658
подробное описание детали  Power and Audio Management Unit for Portable Devices
PDF  158 Pages
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производитель  AMSCO [ams AG]
домашняя страница  http://www.ams.com
Logo AMSCO - ams AG

AS3658 датащи(HTML) 37 Page - ams AG

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Revision 1v13
36 - 157
AS3658
Data Sheet Confidential - Detail ed Descri ption-Power Management Functions
The gpio block includes an internal programmable PWM generator (can be connected to any of the GPIO1_CURR1 …
GPIO4_CURR4 outputs). Its timing is defined by the following tables:
Table 29. PWM Frequency Control High Time Registers
Addr: 56
PWM Frequency Control High Time Registers
This register controls the PWM high time
Bit
Bit Name
Default Access
Description
Table 30. PWM Frequency Control Low Time Registers
Addr: 57
PWM Frequency Control Low Time Registers
This register controls the PWM Low time
Bit
Bit Name
Default Access
Description
Table 31. PWM Divider Registers bits
Addr: 58
CURR control
This register controls the PWM divider
Bit
Bit Name
Default Access
Description
All Step Down DCDC converters and several LDOs can be directly on/off controlled by CURR3_GPIO3 or
CURR4_GPIO4. The CURR3_GPIO3 and/or CURR4_GPIO4 pin should be set to digital input mode (GPIO3Mode =
010b, GPIO4Mode = 010b) and the following register should be set accordingly:
7:0
pwm_h_time
00h
R/W
This bit defines the high time of the pwm generator in
2/fclk_int units
0
pwm_div * 2/ fclk_int
1
pwm_div * 4/ fclk_int
2
pwm_div * 6/ fclk_int
....
FFh
pwm_div * 512/ fclk_int
7:0
pwm_l_time
00h
R/W
This bit defines the high time of the pwm generator in
2/fclk_int units
0
pwm_div * 2/ fclk_int
1
pwm_div * 4/ fclk_int
2
pwm_div * 6/ fclk_int
....
FFh
pwm_div * 512/ fclk_int
7:6
pwm_div
00h
R/W
This bit defines the divider ratio of the prescaler for the
PWM generator
00
Divide by 1
01
Divide by 2
10
Divide by 4
11
Divide by 16



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