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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AS3658 датащи(PDF) 93 Page - ams AG |
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AS3658 датащи(HTML) 93 Page - ams AG |
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93 / 158 page  www.austriamicrosystems.com Revision 1v13 92 - 157 AS3658 Data Sheet Confidential - Detail ed Descri ption- Audio Functi ons Figure 41. I2S Control Diagram Figure 42. I2S Timing Diagram Table 91. PLL,MCLK Settings I2S_mclk_en I2S_select mclk_invert Description 00 0 I2S_1 selected (PLL used) Internal MCLK synchronized to external LRCLK 00 1 I2S_1 selected (PLL used) Internal LRCLK used, synchronized to external SDI 01 0 I2S_2 selected (PLL used) Internal MCLK synchronized to external LRCLK 01 1 I2S_2 selected (PLL used) Internal LRCLK used, synchronized to external SDI SDI1 SCLK1 LRCLK1 MCLK1 SDI2 SCLK2 LRCLK2 MCLK2 SDO3 SCLK3 LRCLK3 i2s_s elect 0 1 i2s_s elect 0 1 SDO1 i2s _select 0 1 i2s_s elect 0 1 i2s_master_on 0 1 MCLK divider i2s _clk_divider<11:0> PLL rising edge only for PCM com patibility pll_mode 18 Bit DAC mono to stereo conversion f or pc m_mode=1 SDO SCLK LRCLK MCLK 14 Bit ADC SDI SCLK LRCLK MCLK Equalizer * 256 * 64 i2s_lrck_s clk _out_en i2s _master_on Fadc2 pcm_mode samle_rate 0 0 LRCLK / 2 1 0 LRCLK / 4 0 1 LRCLK Sample rate sc lk_invert sc lk _invert LRCLK_out i2s_lrck_sclk_out_en i2s_master_on *2 mc lk 256 ext_mclk i2s_mc lk_en mc lk_invert 0 1 0 1 mclk_invert i2s_lrck_sclk_out_en i2s _master_on sdo_on_mclk1_en SDO s do3_select 0 1 0 1 0 1 mclk_invert i2s_mc lk_out_en i2s_master_on i2s_3_on SPDIF spdif _ctrl<1:0> Audio lef t A udio right Audio lef t A udio right SPDIF I2S_mclk_en 15 2 1 0 17 2 1 0 Left Channel 15 2 1 0 17 2 1 0 Right Channel LRCK SCLK SDATA 16 bit SDATA 18 bit MCLK 64 cycles 64 cycles |
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