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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AS3658 датащи(PDF) 96 Page - ams AG |
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AS3658 датащи(HTML) 96 Page - ams AG |
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96 / 158 page  Table 97. ADC_R Register Addr:80 ADC_R These bits control the Audio ADC volume and functions Bit Bit Name Default Access Description www.austriamicrosystems.com Revision 1v13 95 - 157 AS3658 Data Sheet Confidential - Detail ed Descri ption- Audio Functi ons 9.5 I2S master mode and PCM Mode The digital audio interface can also operate in master mode by using I2S1 interface. The pin MCLK2 is used as clock input in that case. Any input clock between sampling rate and 24MHz may be used as input clock. In Master Mode operation SCLK1 as output has 32 clock cycles for each sample word. SCLK = [MCLK / 4] = [LRCLK * 256 / 4] = LRCK * 64 (EQ 8) Sample Rates In Master Mode the i2smaster control allows programming various sample rates. The master clock is generated from the MCLK2 input. Sampling frequencies from 8kHz to 48kHz can be selected. For certain division ratios between master clock and sample ratio a certain deviation is system inherent. 4:0 adr_vol 00000b R/W volume settings for right ADC input, adjustable in 32 steps @ 1.5dB 00000 -34.5 dB gain 00001 -33 dB gain ..... 11110 10.5 dB gain 11111 12 dB gain 5 adc2dac 0b R/W 0 normal mode 1 use ADC output as DAC input (for testing purposes, equalizer is bypassed) 7:6 adcmux 00b R/W 00 Microphone 01 Line In 10 reserved –do not use 11 Audio Sum (Output of Mixer) Table 98. PLL,i2s_clk_divider settings Sample rate MCLK2 input Divider i2s_clk_divider <10:0> Actual sample rate Error kHz kHz kHz % 2 1 * 2 1 * 2 + = RD f LRCLK MCLK 48,000 12288 126,00 126 48,00 0,00 44,100 12288 137,32 137 44,20 0,23 32,000 12288 190,00 190 32,00 0,00 29,400 12288 206,98 207 29,40 -0,01 24,000 12288 254,00 254 24,00 0,00 22,050 12288 276,64 277 22,02 -0,13 12,000 12288 510,00 510 12,00 0,00 |
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