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AS3658 датащи(PDF) 34 Page - ams AG

номер детали AS3658
подробное описание детали  Power and Audio Management Unit for Portable Devices
PDF  158 Pages
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производитель  AMSCO [ams AG]
домашняя страница  http://www.ams.com
Logo AMSCO - ams AG

AS3658 датащи(HTML) 34 Page - ams AG

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www.austriamicrosystems.com
Revision 1v13
33 - 157
AS3658
Data Sheet Confidential - Detail ed Descri ption-Power Management Functions
4…3
GPIO2IOSF
ROM
R/W
00b
input / output signal is written to or set by GPIO2Bit in
the GPIO Bit register
01b
PWM (O) / WDOG (I)
if used for PWM, pwm_h_time and pwm_l_time
define the high and low time of this output and only
allowed for GPIO2Mode=011b,100b
10b
Battery charging active indication output GPIO2 (O)
If Battery charging = 1 then GPIO2=1
11b
NA
5
GPIO2Invert
ROM
R/W
0
normal polarity of input / output signal
1
inverted polarity of input / output signal
(not possible for PWM out)
7…6
GPIO2Pulls
ROM
R/W
00b
no pull-up or pull-down resistor is enabled in all
modes
01b
pull-down resistor is enabled in digital input mode
(clamp disabled)
10b
pull-up resistor is enabled for
GPIO2Mode=000b,010b,011b,100b (clamp disabled)
11b
enable active clamp circuit for
GPIO2Mode=000b,010b,011b,100b (pull-up/down
disabled)
Table 26. CURR3_GPIO3 Bit definition
Addr: 20
GPIO3
This register controls the mode of the CURR3_GPIO3 Pin
Bit
Bit Name
Default Access
Description
2…0
GPIO3Mode
ROM
R/W
000b
digital open drain NMOS output
001b
digital push-pull output (no PWM out possible)
010b
digital input
011b
digital open drain current sink operation Current
defined by curr3_current
100b
digital open drain switch operation On resistance
defined by curr3_current
101b
to
111b
high impedance
4…3
GPIO3IOSF
ROM
R/W
00b
input / output signal is written to or set by GPIO3Bit
in the GPIO Bit register
01b
PWM (O) / WDOG (I)
if used for PWM, pwm_h_time and pwm_l_time
define the high and low time of this output and only
allowed for GPIO2Mode=011b,100b
10b
GPIO3 control of regulators if regX_gpio = 1 and
regX_on = 1
11b
Touchpen ADC wait input
Table 25. CURR2_GPIO2 Bit definition
Addr: 19
GPIO2
This register controls the mode of the CURR1_GPIO2 Pin
Bit
Bit Name
Default Access
Description



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