AS3658 datasheet(85/158 Pages) AMSCO

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Table 82. Digital LDO (VDIG_1.4) Programming voltage table

Code (d)

Code (b)

VOUT(V)

Code (d)

Code (b)

VOUT(V)

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AS3658

Data Sheet Confidential - Detail ed Descri ption-Power Management Functions

Note: Full performance for Vout

≤ 2.20V; max. 100mA output current for Vout ≤ 2.50V; do not use values Vout>2.50V

8.12.3 Low power LDO (V2_5)

The Low power LDO V2_5 is needed to supply the chip core (analog and digital) of the device. It is designed to get the

lowest possible power consumption, and still offering reasonable regulation characteristics. The regulator has three

supply inputs selecting automatically the higher one. This gives the possibility to supply the chip core either with the

battery or with the charger depending on the conditions. Bulk switch comparators are used to avoid any parasitic

current flow. To ensure high PSRR and stability, a low-ESR ceramic capacitor of min. 1µF must be connected to the

output.

000000

0.75

010110

1.80

000001

0.80

010111

1.80

000010

0.85

011000

1.80

000011

0.90

011001

1.80

000100

0.95

011010

1.80

000101

1.00

011011

1.80

000110

1.05

011100

1.80

000111

1.10

011101

1.80

001000

1.15

011110

1.80

001001

1.20

011111

1.80

001010

1.25

100000

1.50 (do not use)

001011

1.30

100001

1.60 (do not use)

001100

1.35

100010

1.70 (do n0t use)

001101

1.40

100011

1.80 (do not use)

001110

1.45

100100

1.90

001111

1.50

100101

2.00

010000

1.55

100110

2.10

010001

1.60

100111

2.20

010010

1.65

101000

2.30

010011

1.70

101001

2.40

010100

1.75

101010

2.50

010101

1.80

Table 83. Low power LDO (V2_5) Characteristics,VBAT=4V; ILOAD_ext=0; Tamb=25ºC; CLOAD =2.2 µF (Ceramic);

unless otherwise specified

Symbol

Parameter

Min

Typ

Max

Unit

Note

VBAT

Supply voltage rage

2.8

5.5

VCHARGER

415

RON

On resistance

Guaranteed per design

PSRR

Power supply rejection

ratio

f=1kHz

f=100kHz

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