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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SPC5644AF0MLU2 датащи(PDF) 113 Page - Freescale Semiconductor, Inc |
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SPC5644AF0MLU2 датащи(HTML) 113 Page - Freescale Semiconductor, Inc |
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113 / 138 page  MPC5644A Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 113 Figure 23. DSPI classic SPI timing — master, CPHA = 0 4 The actual minimum SCK cycle time is limited by pad performance. 5 For DSPI channels using LVDS output operation, up to 40 MHz SCK cycle time is supported. For non-LVDS output, maximum SCK frequency is 20 MHz. Appropriate clock division must be applied. 6 The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. 7 Timing met when pcssck = 3(01), and cssck =2 (0000). 8 The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. 9 Timing met when ASC = 2 (0000), and PASC = 3 (01). 10 Timing met when pcssck = 3. 11 Timing met when ASC = 3. 12 This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10. Data Last Data First Data First Data Data Last Data SIN SOUT PCSx SCK Output 4 9 12 1 11 10 4 SCK Output (CPOL=0) (CPOL=1) 3 2 Note: Refer to Table 48 for the numbers. |
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