SPC5644AF0MLU2 datasheet(11/138 Pages) FREESCALE

11 / 138 page

MPC5644A Microcontroller Data Sheet, Rev. 7

Freescale Semiconductor

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Supports serial bootloading via FlexCAN bus and eSCI with auto baud rate sensing

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Supports serial bootloading of either Power Architecture code (default) or Freescale VLE code

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Supports booting from calibration bus interface

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Supports censorship protection for internal flash memory

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Provides an option to enable the core watchdog timer

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Provides an option to disable the system watchdog timer

1.4.10

eMIOS

The eMIOS timer module provides the capability to generate or measure events in hardware.

The eMIOS module features include:

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Twenty-four 24-bit wide channels

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3 channels’ internal timebases can be shared between channels

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1 Timebase from eTPU2 can be imported and used by the channels

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Global enable feature for all eMIOS and eTPU timebases

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Dedicated pin for each channel (not available on all package types)

Each channel (0–23) supports the following functions:

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General-purpose input/output (GPIO)

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Single-action input capture (SAIC)

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Single-action output compare (SAOC)

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Output pulse-width modulation buffered (OPWMB)

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Input period measurement (IPM)

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Input pulse-width measurement (IPWM)

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Double-action output compare (DAOC)

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Modulus counter buffered (MCB)

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Output pulse width and frequency modulation buffered (OPWFMB)

1.4.11

eTPU2

The eTPU2 is an enhanced co-processor designed for timing control. Operating in parallel with the host CPU, the eTPU2

processes instructions and real-time input events, performs output waveform generation, and accesses shared data without host

intervention. Consequently, for each timer event, the host CPU setup and service times are minimized or eliminated. A powerful

timer subsystem is formed by combining the eTPU2 with its own instruction and data RAM. High-level assembler/compiler

and documentation allows customers to develop their own functions on the eTPU2.

MPC5644A devices feature the second generation of the eTPU, called eTPU2. Enhancements of the eTPU2 over the standard

eTPU include:

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The Timer Counter (TCR1), channel logic and digital filters (both channel and the external timer clock input

[TCRCLK]) now have an option to run at full system clock speed or system clock / 2.

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Channels support unordered transitions: transition 2 can now be detected before transition 1. Related to this

enhancement, the transition detection latches (TDL1 and TDL2) can now be independently negated by microcode.

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A new User Programmable Channel Mode has been added: the blocking, enabling, service request and capture

characteristics of this channel mode can be programmed via microcode.

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Microinstructions now provide an option to issue Interrupt and Data Transfer requests selected by channel. They can

also be requested simultaneously at the same instruction.

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Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the entry point.

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Channel digital filters can be bypassed.

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