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SPC5644AF0MLU2 датащи(PDF) 90 Page - Freescale Semiconductor, Inc |
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SPC5644AF0MLU2 датащи(HTML) 90 Page - Freescale Semiconductor, Inc |
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90 / 138 page ![]() MPC5644A Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 90 3.11 Temperature sensor electrical characteristics 3.12 eQADC electrical characteristics 8 Proper PC board layout procedures must be followed to achieve specifications. 9 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and either fCS or fDS (depending on whether center spread or down spread modulation is enabled). 10 This value is determined by the crystal manufacturer and board design. For 4 MHz to 40 MHz crystals specified for this PLL, load capacitors should not exceed these limits. 11 Proper PC board layout procedures must be followed to achieve specifications. 12 This parameter is guaranteed by design rather than 100% tested. 13 VIHEXT cannot exceed VRC33 in external reference mode. 14 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). 15 Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz. Table 27. Temperature sensor electrical characteristics Symbol C Parameter Conditions Value Unit min typical max — CC C Temperature monitoring range –40 — 150 °C — CC C Sensitivity — 6.3 — mV/°C — CC P Accuracy TJ = –40 to 150 °C –10 — 10 °C Table 28. eQADC conversion specifications (operating) Symbol C Parameter Value Unit min max fADCLK SR — ADC clock (ADCLK) frequency 2 16 MHz CC CC D Conversion cycles 2+13 128+14 ADCLK cycles TSR CC C Stop mode recovery time1 1 Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time that the ADC is ready to perform conversions.Delay from power up to full accuracy = 8 ms. —10 s fADCLK SR — ADC clock (ADCLK) frequency 2 16 mV |
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