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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SPC5644AF0MLU2 датащи(PDF) 99 Page - Freescale Semiconductor, Inc |
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SPC5644AF0MLU2 датащи(HTML) 99 Page - Freescale Semiconductor, Inc |
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99 / 138 page  MPC5644A Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 99 3.17.2 IEEE 1149.1 interface timing NOTE The Nexus/JTAG Read/Write Access Control/Status Register (RWCS) write (to begin a read access) or the write to the Read/Write Access Data Register (RWD) (to begin a write access) does not actually begin its action until 1 JTAG clock (TCK) after leaving the JTAG Update-DR state. This prevents the access from being performed and therefore will not signal its completion via the READY (RDY) output unless the JTAG controller receives an additional TCK. In addition, EVTI is not latched into the device unless there are clock transitions on TCK. Table 38. JTAG pin AC electrical characteristics1 1 JTAG timing specified at VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.5 V with multi-voltage pads programmed to Low-Swing mode, TA = TL to TH, and CL = 30 pF with DSC = 0b10, SRC = 0b11. These specifications apply to JTAG boundary scan only. See Table 39 for functional specifications. # Symbol C Characteristic Min. Value Max. Value Unit 1tJCYC CC D TCK Cycle Time 100 — ns 2tJDC CC D TCK Clock Pulse Width 40 60 ns 3tTCKRISE CC D TCK Rise and Fall Times (40% - 70%) — 3 ns 4tTMSS, tTDIS CC D TMS, TDI Data Setup Time 5 — ns 5tTMSH, tTDIH CC D TMS, TDI Data Hold Time 25 — ns 6tTDOV CC D TCK Low to TDO Data Valid — 222 2 Pad delay is 8–10 ns. Remainder includes TCK pad delay, clock tree delay logic delay and TDO output pad delay. ns 7tTDOI CC D TCK Low to TDO Data Invalid 0 — ns 8tTDOHZ CC D TCK Low to TDO High Impedance — 22 ns 9tJCMPPW CC D JCOMP Assertion Time 100 — ns 10 tJCMPS CC D JCOMP Setup Time to TCK Low 40 — ns 11 tBSDV CC D TCK Falling Edge to Output Valid — 50 ns 12 tBSDVZ CC D TCK Falling Edge to Output Valid out of High Impedance —50 ns 13 tBSDHZ CC D TCK Falling Edge to Output High Impedance —50 ns 14 tBSDST CC D Boundary Scan Input Valid to TCK Rising Edge 253 3 For 20 MHz TCK. —ns 15 tBSDHT CC D TCK Rising Edge to Boundary Scan Input Invalid 253 —ns |
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