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SPC5644AF0MLU2 датащи(PDF) 89 Page - Freescale Semiconductor, Inc |
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SPC5644AF0MLU2 датащи(HTML) 89 Page - Freescale Semiconductor, Inc |
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89 / 138 page ![]() MPC5644A Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 89 VIHEXT CC T EXTAL input high voltage Crystal Mode12 Vxtal + 0.4 —V T External Reference12, 13 VRC33 /2 + 0.4 VRC33 VILEXT CC T EXTAL input low voltage Crystal Mode12 —Vxtal - 0.4 V T External Reference12, 13 0VRC33 /2 - 0.4 — CC T XTAL load capacitance10 4MHz 5 30 pF 8MHz 5 26 12 MHz 5 23 16 MHz 5 19 20 MHz 5 16 40 MHz 5 8 tlpll CC P PLL lock time 10, 14 —— 200 s tdc CC T Duty cycle of reference —40 60 % fLCK CC T Frequency LOCK range — –6 6 % fsys fUL CC T Frequency un-LOCK range — –18 18 % fsys fCS fDS CC D Modulation Depth Center spread ±0.25 ±4.0 % fsys D Down Spread –0.5 –8.0 fMOD CC D Modulation frequency15 —— 100 kHz 1 Considering operation with PLL not bypassed. 2 All internal registers retain data at 0 Hz. 3 “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked mode. 4 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the fLOR window. 5 fVCO self clock range is 20–150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in enhanced mode. 6 This value is determined by the crystal manufacturer and board design. 7 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the CJITTER percentage for a given interval. Table 26. PLLMRFM electrical specifications (VDDPLL = 1.08 V to 3.6 V, VSS = VSSPLL = 0 V, TA = TL to TH) (continued) Symbol C Parameter Conditions Value Unit min max |
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