SPC5644AF0MLU2 datasheet(17/138 Pages) FREESCALE

17 / 138 page

MPC5644A Microcontroller Data Sheet, Rev. 7

Freescale Semiconductor

— 1 receive FIFO per channel

— Up to 255 entries for each FIFO

•

ECC support

1.4.18

System timers

The system timers include two distinct types of system timer:

•

Periodic interrupts/triggers using the Periodic Interrupt Timer (PIT)

•

Operating system task monitors using the System Timer Module (STM)

1.4.18.1

Periodic interrupt timer (PIT)

The PIT provides five independent timer channels, capable of producing periodic interrupts and periodic triggers. The PIT has

no external input or output pins and is intended to provide system ‘tick’ signals to the operating system, as well as periodic

triggers for eQADC queues. Of the five channels in the PIT, four are clocked by the system clock and one is clocked by the

crystal clock. This one channel is also referred to as Real-Time Interrupt (RTI) and is used to wake up the device from low power

stop mode.

The following features are implemented in the PIT:

•

5 independent timer channels

•

Each channel includes 32-bit wide down counter with automatic reload

•

4 channels clocked from system clock

•

1 channel clocked from crystal clock (wake-up timer)

•

Wake-up timer remains active when System STOP mode is entered; used to restart system clock after predefined

time-out period

•

Each channel optionally able to generate an interrupt request or a trigger event (to trigger eQADC queues) when timer

reaches zero

1.4.18.2

System timer module (STM)

The System Timer Module (STM) is designed to implement the software task monitor as defined by AUTOSAR1. It consists

of a single 32-bit counter, clocked by the system clock, and four independent timer comparators. These comparators produce a

CPU interrupt when the timer exceeds the programmed value.

The following features are implemented in the STM:

•

One 32-bit up counter with 8-bit prescaler

•

Four 32-bit compare channels

•

Independent interrupt source for each channel

•

Counter can be stopped in debug mode

1.4.19

Software watchdog timer (SWT)

The Software Watchdog Timer (SWT) is a second watchdog module to complement the standard Power Architecture watchdog

integrated in the CPU core. The SWT is a 32-bit modulus counter, clocked by the system clock or the crystal clock, that can

provide a system reset or interrupt request when the correct software key is not written within the required time window.

The following features are implemented:

•

32-bit modulus counter

•

Clocked by system clock or crystal clock

1.AUTOSAR: AUTomotive Open System ARchitecture (see http://www.autosar.org)

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