STM32F101ZC datasheet(110/112 Pages) STMICROELECTRONICS

110 / 112 page

Revision history

STM32F101xC, STM32F101xD, STM32F101xE

110/112

Doc ID 14610 Rev 8

21-Jul-2009

Figure 1: STM32F101xC, STM32F101xD and STM32F101xE access

line block diagram modified.

Note 5 updated and Note 4 added in Table 5: High-density

STM32F101xx pin definitions.

VRERINT and TCoeff added to Table 13: Embedded internal reference

voltage.

fHSE_ext min modified in Table 21: High-speed external user clock

characteristics.

Table 23: HSE 4-16 MHz oscillator characteristics modified. Note 1

modified below Figure 19: Typical application with an 8 MHz crystal.

Figure 44: Recommended NRST pin protection modified. CL1 and CL2

replaced by C in Table 23: HSE 4-16 MHz oscillator characteristics and

Table 24: LSE oscillator characteristics (fLSE = 32.768 kHz), notes

modified and moved below the tables.

Table 25: HSI oscillator characteristics modified. Conditions removed

from Table 27: Low-power mode wakeup timings.

Jitter added to Table 28: PLL characteristics.

In Table 31: Asynchronous non-multiplexed SRAM/PSRAM/NOR read

timings: th(BL_NOE) and th(A_NOE) modified.

In Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write

timings: th(A_NWE) and th(Data_NWE) modified.

In Table 33: Asynchronous multiplexed NOR/PSRAM read timings:

th(AD_NADV) and th(A_NOE) modified.

In Table 34: Asynchronous multiplexed NOR/PSRAM write timings:

th(A_NWE) modified.

In Table 35: Synchronous multiplexed NOR/PSRAM read timings:

th(CLKH-NWAITV) modified.

In Table 40: Switching characteristics for NAND Flash read and write

cycles: th(NOE-D) modified.

Table 54: SPI characteristics modified.

CADC and RAIN parameters modified in Table 55: ADC characteristics.

RAIN max values modified in Table 56: RAIN max for fADC = 14 MHz.

Table 59: DAC characteristics modified. Figure 53: 12-bit buffered /non-

buffered DAC added.

Table 66.

Document revision history (continued)

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