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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32F101ZC датащи(PDF) 87 Page - STMicroelectronics |
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STM32F101ZC датащи(HTML) 87 Page - STMicroelectronics |
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87 / 112 page  STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Doc ID 14610 Rev 8 87/112 Table 51. I2C characteristics Symbol Parameter Standard mode I2C(1) 1. Guaranteed by design, not tested in production. Fast mode I2C(1)(2) 2. fPCLK1 must be higher than 2 MHz to achieve standard mode I 2C frequencies. It must be higher than 4 MHz to achieve the fast mode I2C frequencies and it must be a multiple of 10 MHz in order to reach the I2C fast mode maximum clock speed of 400 kHz. Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 1.3 µs tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 ns th(SDA) SDA data hold time 0(3) 3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. 0(4) 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 900(3) tr(SDA) tr(SCL) SDA and SCL rise time 1000 20+0.1Cb 300 tf(SDA) tf(SCL) SDA and SCL fall time 300 300 th(STA) Start condition hold time 4.0 0.6 µs tsu(STA) Repeated Start condition setup time 4.7 0.6 tsu(STO) Stop condition setup time 4.0 0.6 µs tw(STO:STA) Stop to Start condition time (bus free) 4.7 1.3 µs Cb Capacitive load for each bus line 400 400 pF |
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