STM32F101ZC datasheet(93/112 Pages) STMICROELECTRONICS

93 / 112 page

STM32F101xC, STM32F101xD, STM32F101xE

Electrical characteristics

Doc ID 14610 Rev 8

93/112

Equation 1: RAIN max formula:

Table 55.

ADC characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDDA

Power supply

2.4

3.6

VREF+

Positive reference voltage

2.4

VDDA

IVREF

Current on the VREF input

160(1)

Based on characterization, not tested in production.

220(1)

µA

fADC

ADC clock frequency

0.6

MHz

(2)

Guaranteed by design, not tested in production.

Sampling rate

0.05

MHz

fTRIG

(2)

External trigger frequency

fADC = 14 MHz

823

kHz

1/fADC

VAIN

Conversion voltage range(3)

VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on

the package. Refer to Section 3: Pinouts and pin descriptions for further details.

0 (VSSA or VREF-

tied to ground)

VREF+

RAIN

(2)

External input impedance

See Equation

1 and Table 56

for details

RADC

(2)

Sampling switch resistance

CADC

(2)

Internal sample and hold

capacitor

8pF

tCAL

(2)

Calibration time

fADC = 14 MHz

5.9

µs

1/fADC

tlat

(2)

Injection trigger conversion

latency

fADC = 14 MHz

0.214

µs

3(4)

For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 55.

1/fADC

tlatr

(2)

Regular trigger conversion

latency

fADC = 14 MHz

0.143

µs

2(4)

1/fADC

(2)

Sampling time

fADC = 14 MHz

0.107

17.1

µs

1.5

239.5

1/fADC

tSTAB

(2)

Power-up time

µs

tCONV

(2)

Total conversion time

(including sampling time)

fADC = 14 MHz

µs

14 to 252 (tS for sampling +12.5 for

successive approximation)

1/fADC

AIN

ADC

()

--------------------------------------------------------------

ADC

–

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