AM79C972BVCW datasheet(107/130 Pages) AMD

107 / 130 page

Am79C972

107

When MERR is set, INTA is as-

serted if IENA is 1 and the mask

bit MERRM (CSR3, bit 11) is 0.

MERR assertion will set the ERR

bit, regardless of the settings of

IENA and MERRM.

Read/Write accessible always.

MERR is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

MERR

cleared

H_RESET, S_RESET, or by set-

ting the STOP bit.

RINT

Receive Interrupt is set by the

Am79C972 controller after the

last descriptor of a receive frame

has been updated by writing a 0

to the OWNership bit. RINT may

also be set when the first descrip-

tor of a receive frame has been

updated by writing a 0 to the

OWNership bit if the LAPPEN bit

of CSR3 has been set to a 1.

When RINT is set, INTA is assert-

ed if IENA is 1 and the mask bit

RINTM (CSR3, bit 10) is 0.

Read/Write accessible always.

RINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

RINT

cleared

H_RESET, S_RESET, or by set-

ting the STOP bit.

TINT

Transmit Interrupt is set by the

Am79C972 controller after the

OWN bit in the last descriptor of a

transmit frame has been cleared

to indicate the frame has been

sent or an error occurred in the

transmission.

When TINT is set, INTA is assert-

ed if IENA is 1 and the mask bit

TINTM (CSR3, bit 9) is 0.

TINT will not be set if TINTOKD

(CSR5, bit 15) is set to 1 and the

transmission was successful.

Read/Write accessible always.

TINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

TINT

cleared

H_RESET, S_RESET, or by set-

ting the STOP bit.

IDON

Initialization Done is set by the

Am79C972 controller after the

initialization sequence has com-

pleted. When IDON is set, the

Am79C972 controller has read

the initialization block from mem-

ory.

When IDON is set, INTA is as-

serted if IENA is 1 and the mask

bit IDONM (CSR3, bit 8) is 0.

Read/Write accessible always.

IDON is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

IDON

cleared

H_RESET, S_RESET, or by set-

ting the STOP bit.

INTR

Interrupt Flag indicates that one

or more following interrupt caus-

ing

conditions

has

occurred:

EXDINT, IDON, MERR, MISS,

MFCO, RCVCCO, RINT, SINT,

TINT, TXSTRT, UINT, STINT,

MREINT, MCCINT, MIIPDTINT,

MAPINT

and

the

associated

mask

enable

bit

pro-

grammed to allow the event to

cause an interrupt. If IENA is set

to 1 and INTR is set, INTA will be

active. When INTR is set by SINT

or SLPINT, INTA will be active in-

dependent of the state of IENA.

Read accessible always. INTR is

read only. INTR is cleared by

clearing all of the active individual

interrupt bits that have not been

masked out.

IENA

Interrupt Enable allows INTA to

be active if the Interrupt Flag is

set. If IENA = 0, then INTA will be

disabled regardless of the state

of INTR.

Read/Write accessible always.

IENA is set by writing a 1 and

cleared by writing a 0. IENA is

cleared

H_RESET

S_RESET and setting the STOP

bit.

RXON

Receive On indicates that the re-

ceive function is enabled. RXON

is set if DRX (CSR15, bit 0) is set

to 0 after the START bit is set. If

INIT and START are set together,

AM79C972BVCW датащи(PDF) 107 Page - Advanced Micro Devices

AM79C972BVCW датащи(HTML) 107 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL