AM79C972BVCW datasheet(106/130 Pages) AMD

106 / 130 page

106

Am79C972

Am79C972 control registers. A

read access will yield undefined

values.

Read/Write accessible always.

RAP is cleared by H_RESET or

S_RESET and is unaffected by

setting the STOP bit.

Control and Status Registers

The CSR space is accessible by performing accesses

to the RDP (Register Data Port). The particular CSR

that is read or written during an RDP access will depend

upon the current setting of the RAP. RAP serves as a

pointer into the CSR space.

CSR0: Am79C972 Controller Status and Control

Certain bits in CSR0 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR0 and write back

the value just read to clear the interrupt condition.

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

ERR

Error is set by the OR of CERR,

MISS, and MERR. ERR remains

set as long as any of the error

flags are true.

Read accessible always. ERR is

read only. Write operations are

ignored.

RES

Reserved locations. Read/Write

accessible always. Read returns

zero.

CERR

Collision Error is set by the

Am79C972 controller when the

device operates in half-duplex

mode and the collision inputs to

the GPSI port failed to activate

within 20 network bit times after

the chip terminated transmission

(SQE Test). This feature is a

transceiver test feature. CERR

reporting is disabled when the

GPSI port is active and the

Am79C972 controller operates in

full-duplex mode.

When the MII port is selected,

CERR is only reported when the

external PHY is operating as a

half-duplex 10BASE-T PHY.

CERR assertion will not result in

an interrupt being generated.

CERR assertion will set the ERR

bit.

Read/Write accessible always.

CERR is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

CERR

cleared

H_RESET, S_RESET, or by set-

ting the STOP bit.

MISS

Missed Frame is set by the

Am79C972 controller when it has

lost an incoming receive frame

resulting from a Receive Descrip-

tor not being available. This bit is

the only immediate indication that

receive data has been lost since

there is no current receive de-

scriptor.

The

Missed

Frame

Counter (CSR112) also incre-

ments each time a receive frame

is missed.

When MISS is set, INTA is as-

serted if IENA is 1 and the mask

bit MISSM (CSR3, bit 12) is 0.

MISS assertion will set the ERR

bit, regardless of the settings of

IENA and MISSM.

Read/Write accessible always.

MISS is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

MISS

cleared

H_RESET, S_RESET, or by set-

ting the STOP bit.

MERR

Memory Error is set by the

Am79C972 controller when it re-

quests the use of the system in-

terface bus by asserting REQ

and has not received GNT asser-

tion after a programmable length

of time. The length of time in mi-

croseconds before MERR is as-

serted will depend upon the

setting of the Bus Timeout Regis-

ter (CSR100). The default setting

of CSR100 will give a MERR after

153.6

µs of bus latency.

AM79C972BVCW датащи(PDF) 106 Page - Advanced Micro Devices

AM79C972BVCW датащи(HTML) 106 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL