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AM79C970A датащи(PDF) 171 Page - Advanced Micro Devices

номер детали AM79C970A
подробное описание детали  PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
PDF  219 Pages
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производитель  AMD [Advanced Micro Devices]
домашняя страница  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM79C970A датащи(HTML) 171 Page - Advanced Micro Devices

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P R E L I M I N A R Y
AMD
171
Am79C970A
Control and Status Registers (continued)
RAP Addr
Symbol
Default Value
Comments
Use
38
CSR38
uuuu uuuu
NNXDAL: Next Next Transmit Descriptor Address Lower
T
39
CSR39
uuuu uuuu
NNXDAU: Next Next Transmit Descriptor Address Upper
T
40
CSR40
uuuu uuuu
CRBC: Current Receive Byte Count
T
41
CSR41
uuuu uuuu
CRST: Current Receive Status
T
42
CSR42
uuuu uuuu
CXBC: Current Transmit Byte Count
T
43
CSR43
uuuu uuuu
CXST: Current Transmit Status
T
44
CSR44
uuuu uuuu
NRBC: Next Receive Byte Count
T
45
CSR45
uuuu uuuu
NRST: Next Receive Status
T
46
CSR46
uuuu uuuu
POLL: Poll Time Counter
T
47
CSR47
uuuu uuuu
PI: Polling Interval
S
48
CSR48
uuuu uuuu
Reserved
49
CSR49
uuuu uuuu
Reserved
50
CSR50
uuuu uuuu
Reserved
51
CSR51
uuuu uuuu
Reserved
52
CSR52
uuuu uuuu
Reserved
53
CSR53
uuuu uuuu
Reserved
54
CSR54
uuuu uuuu
Reserved
55
CSR55
uuuu uuuu
Reserved
56
CSR56
uuuu uuuu
Reserved
57
CSR57
uuuu uuuu
Reserved
58
CSR58
see reg. desc.
SWS: Software Style
S
59
CSR59
uuuu uuuu
Reserved
60
CSR60
uuuu uuuu
PXDAL: Previous Transmit Descriptor Address Lower
T
61
CSR61
uuuu uuuu
PXDAU: Previous Transmit Descriptor Address Upper
T
62
CSR62
uuuu uuuu
PXBC: Previous Transmit Byte Count
T
63
CSR63
uuuu uuuu
PXST: Previous Transmit Status
T
64
CSR64
uuuu uuuu
NXBA: Next Transmit Buffer Address Lower
T
65
CSR65
uuuu uuuu
NXBAU: Next Transmit Buffer Address Upper
T
66
CSR66
uuuu uuuu
NXBC: Next Transmit Byte Count
T
67
CSR67
uuuu uuuu
NXST: Next Transmit Status
T
68
CSR68
uuuu uuuu
Reserved
69
CSR69
uuuu uuuu
Reserved
70
CSR70
uuuu uuuu
Reserved
71
CSR71
uuuu uuuu
Reserved
72
CSR72
uuuu uuuu
RCVRC: Receive Ring Counter
T
73
CSR73
uuuu uuuu
Reserved
74
CSR74
uuuu uuuu
XMTRC: Transmit Descriptor Ring Counter
T
75
CSR75
uuuu uuuu
Reserved
76
CSR76
uuuu uuuu
RCVRL: Receive Descriptor Ring Length
S
77
CSR77
uuuu uuuu
Reserved
78
CSR78
uuuu uuuu
XMTRL: Transmit Descriptor Ring Length
S
79
CSR79
uuuu uuuu
Reserved
80
CSR80
uuuu 1410
DMATCFW: DMA Transfer Counter and FIFO Watermark
S
81
CSR81
uuuu uuuu
Reserved
82
CSR82
uuuu 0000
DMABAT: Bus Activity Timer
S



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