AM79C970A datasheet(152/219 Pages) AMD

152 / 219 page

AMD

P R E L I M I N A R Y

152

Am79C970A

inputs to the AUI or GPSI ports

within the first 4

µs after every

transmission for the purpose of

SQE testing will not cause the

LEDOUT bit to be set.

Read/Write accessible always.

COLE is cleared by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

BCR9: Full-Duplex Control

Bit

Name

Description

Note that bits 15–0 in this register

are programmable through the

external EEPROM. Reserved

bits and read-only bits should be

programmed to ZERO.

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–3

RES

Reserved locations. Written as

ZEROs and read as undefined.

FDRPAD

Full-Duplex Runt Packet Accept

Disable. When FDRPAD is set to

ONE and full-duplex mode is en-

abled, the PCnet-PCI II controller

will only receive frames that meet

the minimum Ethernet frame

length of 64 bytes. Receive DMA

will not start until at least 64 bytes

or a complete frame have been

received. By default, FDRPAD is

cleared to ZERO. The PCnet-

PCI II controller will accept any

length frame and receive DMA

will start according to the pro-

gramming of the receive FIFO

watermark.

Note

that

there

should not be any runt packets in

a full-duplex network, since the

main cause for runt packets is a

network collision and there are

no collisions in a full-duplex net-

work.

Read/Write accessible always.

FDRPAD

cleared

H_RESET and is not affected by

S_RESET or by setting the

STOP bit.

AUIFD

AUI full-duplex. AUIFD enables

full-duplex operation on the AUI

port. AUIFD is only meaningful if

FDEN (BCR9, bit 0) is set to

ONE. If the FDEN bit is ZERO,

the AUI port will always operate

in half-duplex mode. If FDEN is

set to ONE and AUIFD is set to

ONE, full-duplex operation on

the

AUI

port

enabled.

However, if FDEN is set to ONE

but the AUIFD bit is cleared to

ZERO, the AUI port will always

operate in half-duplex mode.

Read/Write accessible always.

AUIFD is cleared by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

FDEN

Full-duplex Enable. FDEN en-

ables

full-duplex

operation.

When FDEN is set to ONE, the

PCnet-PCI II controller will oper-

ate in full-duplex mode when

either the 10BASE-T or the GPSI

port is enabled. To enable full-

duplex operation on the AUI port,

the AUIFD bit (BCR9, bit1) must

be set to ONE in addition to set-

ting FDEN to ONE. When the

DLNKTST bit (CSR15, bit 12) is

set to ONE, the 10BASE-T port

will operate in half-duplex mode

regardless of the setting of

FDEN.

Effect on the

AUIFD

FDEN

Effect on the

10BASE-T

Effect on the

(bit 1)

(bit 0)

AUI Port

Port

GPSI Port

Half-Duplex

Full-Duplex

Read/Write accessible always.

FDEN is cleared by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

BCR16: I/O Base Address Lower

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–5 IOBASEL

Reserved

locations.

After

H_RESET, the value of these

bits

will

undefined.

The

settings of these bits will have

no effect on any PCnet-PCI II

controller function. It is only in-

cluded for software compatibility

with other PCnet family devices.

Read/Write accessible always.

IOBASEL is not affected by

S_RESET or by setting the

STOP bit.

4–0

RES

Reserved locations. Written as

ZEROs, read as undefined.

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