AM79C970A datasheet(116/219 Pages) AMD

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AMD

P R E L I M I N A R Y

116

Am79C970A

CSR3: Interrupt Masks and Deferral Control

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

RES

Reserved location. Read and

written as ZERO.

BABLM

Babble Mask. If BABLM is set,

the BABL bit will be masked and

unable to set the INTR bit.

Read/Write accessible always.

BABLM is cleared by H_RESET

or S_RESET and is not affected

by STOP.

RES

Reserved location. Read and

written as ZERO.

MISSM

Missed Frame Mask. If MISSM is

set, the MISS bit will be masked

and unable to set the INTR bit.

Read/Write accessible always.

MISSM is cleared by H_RESET

or S_RESET and is not affected

by STOP.

MERRM

Memory Error Mask. If MERRM

is set, the MERR bit will be

masked and unable to set the

INTR bit.

Read/Write accessible always.

MERRM is cleared by H_RESET

or S_RESET and is not affected

by STOP.

RINTM

Receive

Interrupt

Mask.

RINTM is set, the RINT bit will be

masked and unable to set the

INTR bit.

Read/Write accessible always.

RINTM is cleared by H_RESET

or S_RESET and is not affected

by STOP.

TINTM

Transmit

Interrupt

Mask.

TINTM is set, the TINT bit will be

masked and unable to set the

INTR bit.

Read/Write accessible always.

TINTM is cleared by H_RESET

or S_RESET and is not affected

by STOP.

IDONM

Initialization

Done

Mask.

IDONM is set, the IDON bit will be

masked and unable to set the

INTR bit.

Read/Write accessible always.

IDONM is cleared by H_RESET

or S_RESET and is not affected

by STOP.

RES

Reserved location. Read and

written as ZEROs.

DXSUFLO

Disable Transmit Stop on Under-

flow error.

When DXSUFLO is cleared to

ZERO, the transmitter is turned

off when an UFLO error occurs

(CSR0, TXON = 0).

When DXSUFLO is set to ONE,

the

PCnet-PCI

controller

gracefully

recovers

from

UFLO error. It scans the transmit

descriptor ring until it finds the

start of a new frame and starts a

new transmission.

Read/Write accessible always.

DXSUFLO

cleared

H_RESET or S_RESET and is

not affected by STOP.

LAPPEN

Look Ahead Packet Processing

Enable. When set to ONE, the

LAPPEN

bit

will

cause

the

PCnet-PCI II controller to gener-

ate an interrupt following the de-

scriptor write operation to the first

buffer of a receive frame. This

interrupt will be generated in ad-

dition to the interrupt that is gen-

erated following the descriptor

write operation to the last buffer

of a receive packet. The interrupt

will be signaled through the RINT

bit of CSR0.

Setting LAPPEN to ONE also en-

ables the PCnet-PCI II controller

to read the STP bit of receive de-

scriptors. The PCnet-PCI II con-

troller

will

use

the

STP

information to determine where it

should begin writing a receive

packet’s data. Note that while in

this mode, the PCnet-PCI II con-

troller can write intermediate

packet data to buffers whose

descriptors do not contain STP

bits set to ONE. Following the

write to the last descriptor used

by a packet, the PCnet-PCI II

controller will scan through the

next descriptor entries to locate

the next STP bit that is set to

ONE. The PCnet-PCI II controller

will begin writing the next pack-

et’s data to the buffer pointed to

by that descriptor.

Note that because several de-

scriptors may be allocated by the

host for each packet, and not all

messages may need all of the de-

scriptors

that

are

allocated

between descriptors that have

STP set to ONE, then some de-

scriptors/buffers may be skipped

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