AM3703CUS datasheet(202/280 Pages) TI

202 / 280 page

SWPS038-054

cam_xclki

cam_pclk

cam_d[9:0]

SOF

D(0)

D(n-1)

EOF

SOF

D(0)

D(n-1)

EOF

ISP16

ISP17

ISP23

ISP24

ISP18

ISP15

AM3715, AM3703

SPRS616F

– JUNE 2010 – REVISED AUGUST 2011

www.ti.com

Table 6-34. CPI Timing Requirements

—ITU Mode(4) (5)

NO.

PARAMETER

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

ISP17

1 / tc(pclk)

Frequency(1), input pixel clock cam_pclk

MHz

ISP18

tw(pclkH)

Typical pulse duration, input pixel clock cam_pclk high

0.5P(2)

ISP18

tw(pclkL)

Typical pulse duration, input pixel clock cam_pclk low

0.5P(2)

tdc(pclk)

Duty cycle error, input pixel clock cam_pclk

0.5*P(2) -

3.465

6.93

tJ(pclk)

Cycle jitter(3), input pixel clock cam_pclk

0.0649*P

(2)

ISP23

tsu(dV-pclkH)

Setup time, input data cam_d[9:0] valid before input

1.82

3.25

pixel clock cam_pclk rising edge

ISP24

th(pclkH-dV)

Hold time, input data cam_d[9:0] valid after input pixel

1.82

3.25

clock cam_pclk rising edge

(1) Related with the input maximum frequency supported by the ISP module.

(2) P = cam_pclk period in ns

(3) Maximum cycle jitter supported by cam_pclk input clock.

(4) The timing requirements are assured up to the cycle jitter and duty cycle error conditions specified.

(5) See Section 4.3.4, Processor Clocks.

(1)

The unused lines are grounded and the data bus is connected to the lower data lines. However, it is possible to shift the data to 0, 2,

or 4 data internal lanes. The different configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode and cam_d[11:2] or cam_d[9:0] in

10-bit mode.

(2)

The parallel camera in ITU mode supports progressive camera modules.

(3)

In cam_xclki, i can be equal to a or b. See Table 6-22 for ISP15 and ISP16 parameters.

Figure 6-29. CPI

—ITU Mode

202

Timing Requirements and Switching Characteristics

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