AM3703CUS datasheet(204/280 Pages) TI

204 / 280 page

SWPS038-055

dss_pclk

dss_vsync

dss_hsync

dss_acbias

dss_data[23:0]

DL4

DL5

DL3

DL0

DL2

DL1

AM3715, AM3703

SPRS616F

– JUNE 2010 – REVISED AUGUST 2011

www.ti.com

Table 6-36. DSS Switching Characteristics

—TFT Mode(4) (continued)

NO.

PARAMETER

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

DL2

td(pclkA-acbiasA)

Delay time, output pixel clock dss_pclk active edge to

–4.215

4.215

–4.658

4.658

output data enable dss_acbias active level

DL3

td(pclkA-dV)

Delay time, output pixel clock dss_pclk active edge to

–4.215

4.215

–4.658

4.658

output data dss_data[23:0] valid

DL4

1 / tc(pclk)

Frequency(2), output pixel clock dss_pclk

74.3(3)

66(3)

MHz

DL5

tw(pclk)

Pulse duration, output pixel clock dss_pclk low or high

0.45P(1)

0.55P(1)

0.45P(1)

0.55P(1)

(5)

(1) P = dss_pclk period in ns

(2) The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the

DISPC_DIVISOR register.

(3) For the DSS (TFT mode) in HD-TV application, to run at full speed (74.3 MHz) it is recommended to use the dss_data[5:0] signals on

the dss_data[23:18] balls (H26, H25, E28, J26, AC27, AC28). In that case, the dss_data[23:18] signals are available on the sys_boot0,

sys_boot1, sys_boot3, sys_boot4, sys_boot5, and sys_boot6 balls (AH26, AG26, AF18, AF19, AE21, AF21) to run at full speed (74.3

MHz).

If the dss_data[5:0] signals are used on the dss_data[5:0] balls (AG22, AH22, AG23, AH23, AG24, AH24), OPP100 DSS (TFT mode)

are limited at 66 MHz. The values may change following the silicon characterization result.

(4) See Section 4.3.4, Processor Clocks.

(5) tW(pclk) = 0.66.P when DISPC_DIVISOR[6:0] PCD = 3.

(1)

The pixel data bus depends on the use of 8-, 9-, 12-, 16-, 18-, or 24-bit per pixel data output pins.

(2)

The pixel clock frequency is programmable.

(3)

All timings not illustrated in the waveform are progammable by software, and control signal polarity and driven edge of dss_pclk too.

(4)

For more information, see the DSS chapter in the AM/DM37x Multimedia Device Technical Reference Manual (literature number

SPRUGN4).

Figure 6-30. DSS

—TFT Mode

6.5.2.1.3 DSS

—Parallel Interface—Bypass Mode—STN Mode

Table 6-38 assumes testing over the recommended operating conditions and electrical characteristic

conditions below (see Figure 6-31).

Table 6-37. DSS Timing Conditions

—STN Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

MIN

MAX

Output Condition

CLOAD

Output load capacitance(1)

204

Timing Requirements and Switching Characteristics

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