AM3703CUS datasheet(205/280 Pages) TI

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SWPS038-056

dss_pclk

dss_vsync

dss_hsync

dss_acbias

dss_data[23:0]

DL4

DL5

DL3

AM3715, AM3703

www.ti.com

SPRS616F

– JUNE 2010 – REVISED AUGUST 2011

(1) Buffer strength configuration: LB0 = 1

Table 6-38. DSS Switching Characteristics

—STN Mode(3) (4)

NO.

PARAMETER

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

DL3

td(pclkA-dV)

Delay time, output pixel clock dss_pclk active

–6.868

6.868

–6.868

6.868

edge to output data dss_data[7:0] valid

DL4

1 / tc(pclk)

Frequency(2), output pixel clock dss_pclk

MHz

DL5

tw(pclk)

Pulse duration, output pixel clock dss_pclk low

0.45P(1)

0.55P(1) (5)

0.45P(1)

0.55P(1)(5)

or high

(1) P = dss_pclk period in ns

(2) The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the

DISPC_DIVISOR register.

(3) The DSS in STN mode is used with 4 or 8 pins only; unused pixel data bits always remain low.

(4) See Section 4.3.4, Processor Clocks.

(5) tW(pclk) = 0.66P when DISPC_DIVISOR[6:0] PCD = 3.

(1)

The pixel data bus depends on the use of 4-, 8-, 12-, 16-, 18-, or 24-bit per pixel data output pins.

(2)

All timings not illustrated in the waveform are progammable by software, and control signal polarity and driven edge of dss_pclk too.

(3)

dss_vsync width must be programmed to be as small as possible.

(4)

The pixel clock frequency is programmable.

(5)

For more information, see the DSS chapter in the AM/DM37x Multimedia Device Technical Reference Manual (literature number

SPRUGN4).

Figure 6-31. DSS

—STN Mode

6.5.2.2

DSS

—Parallel Interface— RFBI Mode — Applications

6.5.2.2.1 DSS

—Parallel Interface—RFBI Mode— MIPI DBI-B 2.0 —LCD Panel

The Remote Frame Buffer Interface (RFBI) module provides the necessary control signals and data

(MIPI

® DBI 2.0 type B protocol) to interface to the LCD driver of the LCD panel.

Table 6-40 and Table 6-41 assume testing over the recommended operating conditions and electrical

characteristic conditions below (see Figure 6-32 through Figure 6-34).

Timing Requirements and Switching Characteristics

205

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