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Military ProASIC3/EL Low Power Flash FPGAs

Revision 3

3-3

Globals

GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the

global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have

identical capabilities. Unused GL pins are configured as inputs with pull-up resistors.

See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits in Low Power

Flash Devices and Mixed Signal FPGAs " chapter of the Military ProASIC3/EL FPGA Fabric User’s

Guide. All inputs labeled GC/GF are direct inputs into the quadrant clocks. For example, if GAA0 is used

for an input, GAA1 and GAA2 are no longer available for input to the quadrant globals. All inputs labeled

GC/GF are direct inputs into the chip-level globals, and the rest are connected to the quadrant globals.

The inputs to the global network are multiplexed, and only one input can be used as a global input.

Refer to the "I/O Structures in IGLOO and ProASIC3 Devices" chapter (for A3P250 and A3P1000) or "I/O

Structures in IGLOOe and ProASIC3E Devices" (for A3PE600L and A3PE3000L) of the Military

ProASIC3/EL FPGA Fabric User’s Guide for an explanation of the naming of global pins.

Flash*Freeze Mode Activation Pin

Flash*Freeze is available on A3PE600L and A3PE3000L devices. The FF pin is a dedicated input pin

used to enter and exit Flash*Freeze mode. The FF pin is active low, has the same characteristics as a

single-ended I/O, and must meet the maximum rise and fall times. When Flash*Freeze mode is not used

in the design, the FF pin is available as a regular I/O. The FF pin can be configured as a Schmitt trigger

input.

When Flash*Freeze mode is used, the FF pin must not be left floating to avoid accidentally entering

Flash*Freeze mode. While in Flash*Freeze mode, the Flash*Freeze pin should be constantly asserted.

The Flash*Freeze pin can be used with any single-ended I/O standard supported by the I/O bank in

which the pin is located, and input signal levels compatible with the I/O standard selected. The FF pin

should be treated as a sensitive asynchronous signal. When defining pin placement and board layout,

simultaneously switching outputs (SSOs) and their effects on sensitive asynchronous pins must be

considered.

Unused FF or I/O pins are tristated with weak pull-up. This default configuration applies to both

Flash*Freeze mode and normal operation mode. No user intervention is required.

Table 3-1 shows the Flash*Freeze pin location on the available packages for Military ProASIC3/EL

devices. The Flash*Freeze pin location is independent of device, allowing migration to larger or smaller

devices while maintaining the same pin location on the board. Refer to the "Flash*Freeze Technology

and Low Power Modes" chapter of the Military ProASIC3/EL FPGA Fabric User’s Guide for more

information on I/O states during Flash*Freeze mode.

Table 3-1 • Flash*Freeze Pin Location in Military ProASIC3/EL Packages (device-independent)

Military ProASIC3/EL Packages

Flash*Freeze Pin

FG484

FG896

AH4

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