MPC8241EC datasheet(15/58 Pages) FREESCALE

15 / 58 page

MPC8241 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Electrical and Thermal Characteristics

Figure 6 shows the PCI_SYNC_IN input clock timing diagram, and Figure 7 through Figure 10 show the

DLL locking range loop delay versus frequency of operation.

Figure 6. PCI_SYNC_IN Input Clock Timing Diagram

OSC_IN frequency stability

—

100

ppm

Notes:

1. Rise and fall times for the PCI_SYNC_IN input are measured from 0.4 through 2.4 V.

2. Specification value at maximum frequency of operation.

3. Pin-to-pin skew includes quantifying the additional amount of clock skew (or jitter) from the DLL besides any intentional skew

added to the clocking signals from the variable length DLL synchronization feedback loop, that is, the amount of variance

between the internal sys_logic_clk and the SDRAM_SYNC_IN signal after the DLL is locked. While pin-to-pin skew between

SDRAM_CLKs can be measured, the relationship between the internal sys_logic_clk and the external SDRAM_SYNC_IN

cannot be measured and is guaranteed by design.

4. Relock time is guaranteed by design and characterization. Relock time is not tested.

5. Relock timing is guaranteed by design. PLL-relock time is the maximum amount of time required for PLL lock after a stable

VDD and PCI_SYNC_IN are reached during the reset sequence. This specification also applies when the PLL has been

disabled and subsequently re-enabled during sleep mode. Also note that HRST_CPU/HRST_CTRL must be held asserted

for a minimum of 255 bus clocks after the PLL-relock time during the reset sequence.

6. DLL_EXTEND is bit 7 of the PMC2 register <72>. N is a non-zero integer (see Figure 7 through Figure 10). Tclk is the period

of one SDRAM_SYNC_OUT clock cycle in ns. Tloop is the propagation delay of the DLL synchronization feedback loop (PC

board runner) from SDRAM_SYNC_OUT to SDRAM_SYNC_IN in ns; 6.25 inches of loop length (unloaded PC board runner)

corresponds to approximately 1 ns of delay. For details about how Figure 7 through Figure 10 may be used, refer to the

Freescale application note AN2164, MPC8245/MPC8241 Memory Clock Design Guidelines, for details on MPC8241 memory

clock design.

7. Rise and fall times for the OSC_IN input are guaranteed by design and characterization. OSC_IN input rise and fall times are

not tested.

Table 8. Clock AC Timing Specifications (continued)

At recommended operating conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V

Num

Characteristics and Conditions

Min

Max

Unit

Notes

VM = Midpoint Voltage (1.4 V)

CVIL

CVIH

PCI_SYNC_IN

MPC8241EC датащи(PDF) 15 Page - Freescale Semiconductor, Inc

MPC8241EC датащи(HTML) 15 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

датащи скачать

ссылки URL