MPC8241EC datasheet(40/58 Pages) FREESCALE

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MPC8241 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

PLL Configuration

1111014

Not usable

Off

1111114

Not usable

Off

Notes:

1. PLL_CFG[0:4] settings not listed are reserved. Bits 7–4 of register offset <0xE2> contain the PLL_CFG[0:4] setting value.

Note the impact of the relevant revisions for mode 7.

2. Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity.

3. Limited by maximum PCI input frequency (66 MHz).

4. Limited by minimum CPU VCO frequency (300 MHz).

5. Limited by maximum CPU operating frequency.

6. In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL is

disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for hardware modeling. The

AC timing specifications in this document do not apply in PLL bypass mode.

7. Limited by minimum CPU operating frequency (100 MHz).

8. Limited due to maximum memory VCO frequency (352 MHz).

9. In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the peripheral logic PLL

is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation. In this mode, the OSC_IN input signal

clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode operation, and the processor PLL is disabled. The

PCI_SYNC_IN and OSC_IN input clocks must be externally synchronized. This mode is intended for hardware modeling.

The AC timing specifications in this document do not apply in dual PLL bypass mode.

10.Limited by maximum CPU VCO frequency (704 MHz).

11.Limited by maximum system memory interface operating frequency (83 MHz @ 166 MHz CPU bus speed).

12.Limited by maximum system memory interface operating frequency (100 MHz @ 200 MHz CPU bus speed).

13.Limited by minimum memory VCO frequency (132 MHz).

14.In clock off mode, no clocking occurs inside the MPC8241, regardless of the PCI_SYNC_IN input.

Table 18. PLL Configurations (266-MHz Parts)

Ref 2

PLL_

CFG[0:4] 10,11

266-MHz Part 9

Multipliers

PCI Clock Input

(PCI_SYNC_IN)

Range 1

(MHz)

Periph Logic/

Mem Bus

Clock Range

(MHz)

CPU Clock

Range

(MHz)

PCI-to-Mem

(Mem VCO)

Mem-to-CPU

(CPU VCO)

00000

25–355

75–105

188–263

3 (2)

2.5 (2)

00001

25–295

75–88

225–264

3 (2)

00010

5015–595

50–59

225–266

1 (4)

4.5 (2)

0001112

5014–661

50–66

100–133

1 (Bypass)

2 (4)

00100

25–444

50–88

100–176

2 (4)

Table 17. PLL Configurations (166- and 200-MHz) (continued)

Ref 2

PLL_CFG

[0:4] 1

166 MHz-Part 2

200-MHz Part 2

Multipliers

PCI Clock

Input

(PCI_

SYNC_IN)

Range 3

(MHz)

Peripheral

Logic/

Mem

Bus Clock

Range

(MHz)

CPU

Clock

Range

(MHz)

PCI Clock

Input

(PCI_

SYNC_IN)

Range 3

(MHz)

Peripheral

Logic/

Mem Bus

Clock

Range

(MHz)

CPU

Clock

Range

(MHz)

PCI-to-

Mem

(Mem VCO)

Mem-to-

CPU

(CPU VCO)

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