MPC8241EC datasheet(44/58 Pages) FREESCALE

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MPC8241 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

System Design Information

7.4

Pull-Up/Pull-Down Resistor Requirements

The data bus input receivers are normally turned off when no read operation is in progress; therefore, they

do not require pull-up resistors on the bus. The data bus signals are: MDH[0:31], MDL[0:31], and

PAR[0:7].

If the 32-bit data bus mode is selected, the input receivers of the unused data and parity bits (MDL[0:31]

and PAR[4:7]) are disabled, and their outputs drive logic zeros when they would otherwise be driven. For

this mode, these pins do not require pull-up resistors and should be left unconnected to minimize possible

output switching.

The TEST0 pin requires a pull-up resistor of 120

Ω or less connected to GVDD_OVDD.

RTC should have weak pull-up resistors (2–10 k

Ω) connected to GV

DD_OVDD and that the following

signals should be pulled up to GVDD_OVDD with weak pull-up resistors (2–10 kΩ): SDA, SCL, SMI,

SRESET/SDMA12, TBEN/SDMA13, CHKSTOP_IN/SDMA14, TRIG_IN/RCS2, QACK/DA0, and

DRDY.

The following PCI control signals should be pulled up to LVDD (the clamping voltage) with weak pull-up

resistors (2–10 k

Ω): DEVSEL, FRAME, IRDY, LOCK, PERR, SERR, STOP, and TRDY. The resistor

values may need to have stronger adjustment to reduce induced noise on specific board designs.

The following pins have internal pull-up resistors enabled at all times: REQ[3:0], REQ4/DA4, TCK, TDI,

TMS, and TRST. See Table 16.

The following pins have internal pull-up resistors that are enabled only while the device is in the reset state:

GNT4/DA5, MDL0, FOE, RCS0, SDRAS, SDCAS, CKE, AS, MCP, MAA[0:2], and PMAA[0:2]. See

Table 16.

The following pins are reset configuration pins: GNT4/DA5, MDL[0], FOE, RCS0, CKE, AS, MCP,

QACK/DA0, MAA[0:2], PMAA[0:2], SDMA[1:0], MDH[16:31], and PLL_CFG[0:4]/DA[10:15]. These

pins are sampled during reset to configure the device. The PLL_CFG[0:4] signals are sampled a few clocks

after the negation of HRST_CPU and HRST_CTRL.

Reset configuration pins should be tied to GND by means of 1-k

Ω pull-down resistors to ensure that a logic

zero level is read into the configuration bits during reset if the default logic-one level is not desired.

Any other unused active low input pins should be tied to a logic-one level by means of weak pull-up

resistors (2–10 k

Ω) to the appropriate power supply listed in Table 16. Unused active high input pins

should be tied to GND by means of weak pull-down resistors (2–10 k

Ω).

7.5

PCI Reference Voltage—LVDD

The MPC8241 PCI reference voltage (LVDD) pins should be connected to 3.3 ± 0.3 V power supply if

interfacing the MPC8241 into a 3.3-V PCI bus system. Similarly, the LVDD pins should be connected to

5.0 V ± 5% power supply if interfacing the MPC8241 into a 5-V PCI bus system. For either reference

voltage, the MPC8241 always performs 3.3-V signaling as described in the PCI Local Bus Specification

(Rev. 2.2). The MPC8241 tolerates 5-V signals when interfaced into a 5-V PCI bus system. (See Errata

No. 18 in the MPC8245/MPC8241 Integrated Processor Chip Errata).

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