MPC8241EC datasheet(14/58 Pages) FREESCALE

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MPC8241 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Electrical and Thermal Characteristics

Table 7 provides the operating frequency information for the MPC8241 at recommended operating

conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V.

4.5.1

Clock AC Specifications

Table 8 provides the clock AC timing specifications at recommended operating conditions, as defined in

Section 4.5.2, “Input AC Timing Specifications.” These specifications are for the default driver strengths

indicated in Table 4. Figure 6 shows the PCI_SYNC_IN input clock timing diagram with the labeled

number items listed in Table 8.

Table 7. Operating Frequency

Characteristic

166 MHz

200 MHz

266 MHz

Unit

VDD/AVDD/AVDD2 = 1.8 ± 100 mV

Min

Max

Min

Max

Min

Max

Processor frequency (CPU)

100

166

100

200

100

266

MHz

Memory bus frequency

100

133

MHz

PCI input frequency

25–66

MHz

Caution: The PCI_SYNC_IN frequency and PLL_CFG[0:4] settings must be chosen such that the resulting peripheral

logic/memory bus frequency and CPU (core) frequencies do not exceed their respective maximum or minimum operating

frequencies. Refer to the PLL_CFG[0:4] signal description in Section 6, “PLL Configuration,” for valid PLL_CFG[0:4] settings

and PCI_SYNC_IN frequencies.

Table 8. Clock AC Timing Specifications

At recommended operating conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V

Num

Characteristics and Conditions

Min

Max

Unit

Notes

Frequency of operation (PCI_SYNC_IN)

MHz

2, 3

PCI_SYNC_IN rise and fall times

—

2.0

PCI_SYNC_IN duty cycle measured at 1.4 V

PCI_SYNC_IN pulse width high measured at 1.4 V

PCI_SYNC_IN pulse width low measured at 1.4 V

PCI_SYNC_IN jitter

—

200

PCI_CLK[0:4] skew (pin-to-pin)

—

250

SDRAM_CLK[0:3] skew (pin-to-pin)

—

190

Internal PLL relock time

—

100

µs

2, 4, 5

DLL lock range with DLL_EXTEND = 0 (disabled) and

normal tap delay; (default DLL mode)

See Figure 7

DLL lock range for other modes

See Figure 8 through Figure 10

Frequency of operation (OSC_IN)

MHz

OSC_IN rise and fall times

—

OSC_IN duty cycle measured at 1.4 V

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