MPC8241EC datasheet(46/58 Pages) FREESCALE

46 / 58 page

MPC8241 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

System Design Information

Figure 27. COP Connector Diagram

HRESET 7

HRST_CPU

HRST_CTRL

From Target

Board Sources

HRESET

SRESET 5

VDD_SENSE

5 2

15 3

1 k

10 k

OVDD

CHKSTOP_IN 6

TMS

TDO

TDI

TCK

TMS

TDO

TDI

TCK

TRST

(if any)

14 4

Key

Notes:

1. QACK is an output and is not required at the COP header for emulation.

2. RUN/STOP normally on pin 5 of the COP header is not implemented on the MPC8241.

Connect pin 5 of the COP header to OVDD with a 1- kΩ pull-up resistor.

3. CKSTP_OUT normally on pin 15 of the COP header is not implemented on the MPC8241.

Connect pin 15 of the COP header to OVDD with a 10-kΩ pull-up resistor.

4. Pin 14 is not physically present on the COP header.

QACK 1

OVDD

10 k

OVDD

TRST 7

10 k

OVDD

10 k

5. SRESET functions as output SDMA12 in extended ROM mode.

6. CHKSTOP_IN functions as output SDMA14 in extended ROM mode.

MPC8241

KEY

No pin

COP Connector

Physical Pin Out

7. The COP port and target board should be able to independently assert HRESET and TRST to

the processor to fully control the processor as shown.

8. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP

header through an AND gate to TRST of the part. If the JTAG interface is not implemented, connect

HRESET from the target source to TRST of the part through a 0-

Ω isolation resistor.

Ω 8

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