PIC16F87 datasheet(104/230 Pages) MICROCHIP

104 / 230 page

PIC16F87/88

DS30487D-page 104

 2002-2013 Microchip Technology Inc.

11.2.2

AUSART ASYNCHRONOUS

RECEIVER

The receiver block diagram is shown in Figure 11-4.

The data is received on the RB2/SDO/RX/DT pin and

drives the data recovery block. The data recovery block

is actually a high-speed shifter, operating at x16 times

the baud rate; whereas, the main receive serial shifter

operates at the bit rate or at FOSC.

Once Asynchronous mode is selected, reception is

enabled by setting bit CREN (RCSTA<4>).

The heart of the receiver is the Receive (Serial) Shift

received data in the RSR is transferred to the RCREG

bit, RCIF (PIR1<5>), is set. The actual interrupt can be

enabled/disabled by setting/clearing enable bit RCIE

(PIE1<5>). Flag bit RCIF is a read-only bit which is

cleared by the hardware. It is cleared when the RCREG

double-buffered register (i.e., it is a two-deep FIFO). It

is possible for two bytes of data to be received and

transferred to the RCREG FIFO and a third byte to

begin shifting to the RSR register. On the detection of

the Stop bit of the third byte, if the RCREG register is

still full, the Overrun Error bit, OERR (RCSTA<1>), will

be set. The word in the RSR will be lost. The RCREG

the FIFO. Overrun bit OERR has to be cleared in soft-

ware. This is done by resetting the receive logic (CREN

is cleared and then set). If bit OERR is set, transfers

from the RSR register to the RCREG register are inhib-

ited and no further data will be received. It is, therefore,

essential to clear error bit OERR if it is set. Framing

Error bit, FERR (RCSTA<2>), is set if a Stop bit is

detected as clear. Bit FERR and the 9th receive bit are

buffered the same way as the receive data. Reading

the RCREG will load bits RX9D and FERR with new

values; therefore, it is essential for the user to read the

RCSTA register, before reading the RCREG register, in

order not to lose the old FERR and RX9D information.

FIGURE 11-4:

AUSART RECEIVE BLOCK DIAGRAM

FIGURE 11-5:

ASYNCHRONOUS RECEPTION

x64 Baud Rate CLK

SPBRG

Baud Rate Generator

RB2/SDO/RX/DT

Pin Buffer

and Control

SPEN

Data

Recovery

CREN

OERR

FERR

RSR Register

MSb

LSb

RX9D

RCREG Register

FIFO

Interrupt

RCIF

RCIE

Data Bus

64

16

Stop

Start

(8)

RX9



FOSC

Start

bit

bit 7/8

bit 1

bit 0

bit 7/8

bit 0

Stop

bit

Start

bit

Start

bit

bit 7/8

Stop

bit

RX pin

Reg

Rcv Buffer Reg

Rcv Shift

Read Rcv

Buffer Reg

RCREG

RCIF

(Interrupt Flag)

OERR bit

CREN

Word 1

RCREG

Word 2

RCREG

Stop

bit

Note:

This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word,

causing the OERR (Overrun) bit to be set.

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