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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC16LC712 датащи(PDF) 10 Page - Microchip Technology |
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PIC16LC712 датащи(HTML) 10 Page - Microchip Technology |
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10 / 106 page  PIC16C712/716 DS41106C-page 10 1999-2013 Microchip Technology Inc. 2.2 Data Memory Organization The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits. = 00 Bank 0 = 01 Bank 1 = 10 Bank 2 (not implemented) = 11 Bank 3 (not implemented) Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Regis- ters are General Purpose Registers, implemented as static RAM. All implemented banks contain Special Function Registers. Some “high use” Special Function Registers from one bank may be mirrored in another bank for code reduction and quicker access. 2.2.1 GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly, or indirectly through the File Select Register FSR (see Section 2.5 “Indirect Addressing, INDF and FSR Registers”). FIGURE 2-3: REGISTER FILE MAP RP1(1) RP0 (STATUS<6:5>) Note 1: Maintain this bit clear to ensure upward compatibility with future products. Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. File Address File Address 00h INDF(1) INDF(1) 80h 01h TMR0 OPTION_REG 81h 02h PCL PCL 82h 03h STATUS STATUS 83h 04h FSR FSR 84h 05h PORTA TRISA 85h 06h PORTB TRISB 86h 07h DATACCP TRISCCP 87h 08h 88h 09h 89h 0Ah PCLATH PCLATH 8Ah 0Bh INTCON INTCON 8Bh 0Ch PIR1 PIE1 8Ch 0Dh 8Dh 0Eh TMR1L PCON 8Eh 0Fh TMR1H 8Fh 10h T1CON 90h 11h TMR2 91h 12h T2CON PR2 92h 13h 93h 14h 94h 15h CCPR1L 95h 16h CCPR1H 96h 17h CCP1CON 97h 18h 98h 19h 99h 1Ah 9Ah 1Bh 9Bh 1Ch 9Ch 1Dh 9Dh 1Eh ADRES 9Eh 1Fh ADCON0 ADCON1 9Fh 20h General Purpose Registers 96 Bytes General Purpose Registers 32 Bytes A0h BFh C0h 7Fh FFh Bank 0 Bank 1 |
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