PIC16LC712 datasheet(65/106 Pages) MICROCHIP

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DS41106C-page 65

PIC16C712/716

When the SLEEP instruction is being executed, the next

instruction (PC + 1) is pre-fetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set (enabled). Wake-up is

regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEP instruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction and then branches to the inter-

rupt address (0004h). In cases where the execution of

the instruction following SLEEP is not desirable, the

user should have a NOP after the SLEEP instruction.

9.13.2

WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

• If the interrupt occurs before the execution of a

SLEEP

instruction, the SLEEP instruction will

complete as a NOP. Therefore, the WDT and WDT

postscaler will not be cleared, the TO bit will not

be set and PD bits will not be cleared.

• If the interrupt occurs during or after the execu-

tion of a SLEEP instruction, the device will imme-

diately wake-up from Sleep. The SLEEP

instruction will be completely executed before the

wake-up. Therefore, the WDT and WDT

postscaler will be cleared, the TO bit will be set

and the PD bit will be cleared.

Even if the flag bits were checked before executing a

SLEEP

instruction, it may be possible for flag bits to

become set before the SLEEP instruction completes. To

determine whether a SLEEP instruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

To ensure that the WDT is cleared, a CLRWDT instruc-

tion should be executed before a SLEEP instruction.

FIGURE 9-17:

WAKE-UP FROM SLEEP THROUGH INTERRUPT

9.14

Program Verification/Code

Protection

the

code

protection

bit(s)

have

not

been

programmed, the on-chip program memory can be

read out for verification purposes.

9.15

ID Locations

Four memory locations (2000h-2003h) are designated

as ID locations where the user can store checksum or

other code-identification numbers. These locations are

not accessible during normal execution, but are read-

able

and

writable

during

Program/Verify.

recommended that only the 4 Least Significant bits of

the ID location are used.

For ROM devices, these values are submitted along

with the ROM code.

Q3 Q4

Q1 Q2

Q2 Q3 Q4

Q1 Q2 Q3 Q4

Q2 Q3

Q1 Q2

OSC1

CLKOUT(4)

INT pin

INTF flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

fetched

Instruction

executed

PC + 1

PC + 2

Inst(PC) = Sleep

Inst(PC - 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Interrupt Latency

(Note 2)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Dummy cycle

PC + 2

0004h

0005h

Dummy cycle

TOST(2)

PC + 2

Note 1:

XT, HS or LP Oscillator mode assumed.

TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC Osc mode.

GIE = 1 assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.

CLKOUT is not available in these osc modes, but shown here for timing reference.

Note:

Microchip does not recommend code

protecting windowed devices.

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