PIC16LC712 datasheet(48/106 Pages) MICROCHIP

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PIC16C712/716

DS41106C-page 48

 1999-2013 Microchip Technology Inc.

8.1

A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,

the Charge Holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 8-4. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge

the capacitor CHOLD. The sampling switch (RSS)

impedance varies over the device voltage (VDD). The

source impedance affects the offset voltage at the

analog input (due to pin leakage current). The

maximum recommended impedance for analog

sources is 10 k

. After the analog input channel is

selected (changed) this acquisition must be done

before the conversion can be started.

To calculate the minimum acquisition time, TACQ, see

the PIC® Mid-Range Reference Manual, (DS33023).

This equation calculates the acquisition time to within

1/2 LSb error (512 steps for the A/D). The 1/2 LSb error

is the maximum error allowed for the A/D to meet its

specified accuracy.

FIGURE 8-4:

ANALOG INPUT MODEL

Note:

When the conversion is started, the hold-

ing capacitor is disconnected from the

input pin.

CPIN

ANx

5 pF

VDD

VT = 0.6V

I leakage

RIC

 1k

Sampling

Switch

RSS

CHOLD

= DAC capacitance

VSS

Sampling Switch

567 8 9 10 11

)

VDD

= 51.2 pF

 500 nA

Legend: CPIN

I leakage

RIC

CHOLD

= input capacitance

= threshold voltage

= leakage current at the pin due to

= interconnect resistance

= sampling switch

= sample/hold capacitance (from DAC)

various junctions

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