LPC81XM datasheet(12/67 Pages) NXP

номер детали	LPC81XM

подробное описание детали	32-bit ARM Cortex-M0 microcontroller; up to 16 kB flash and 4 kB SRAM

PDF	67 Pages

Scroll/Zoom	100%

производитель	NXP [NXP Semiconductors]

домашняя страница	http://www.nxp.com

Logo

12 / 67 page

LPC81xM

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1.0 — 7 November 2012

12 of 67

NXP Semiconductors

LPC81xM

32-bit ARM Cortex-M0+ microcontroller

Up to eight pins, regardless of the selected function, can be programmed to generate an

interrupt on a level, a rising or falling edge, or both. The interrupt generating pins can be

selected from all digital or mixed digital/analog pins. The pin interrupt/pattern match block

controls the edge or level detection mechanism.

7.6 System tick timer

The ARM Cortex-M0+ includes a 24-bit system tick timer (SysTick) that is intended to

generate a dedicated SysTick exception at a fixed time interval (typically 10 ms).

7.7 Memory map

The LPC81xM incorporates several distinct memory regions. Figure 6 shows the overall

map of the entire address space from the user program viewpoint following reset. The

interrupt vector area supports address remapping.

The ARM private peripheral bus includes the ARM core registers for controlling the NVIC,

the system tick timer (SysTick), and the reduced power modes.

LPC81XM датащи(PDF) 12 Page - NXP Semiconductors