LPC81XM datasheet(53/67 Pages) NXP

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LPC81xM

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Objective data sheet

Rev. 1.0 — 7 November 2012

53 of 67

NXP Semiconductors

LPC81xM

32-bit ARM Cortex-M0+ microcontroller

In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF

(Figure 30), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This

corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.

The XTALOUT pin in this configuration can be left unconnected.

External components and models used in oscillation mode are shown in Figure 31 and in

Table 25 and Table 26. Since the feedback resistance is integrated on chip, only a crystal

and the capacitances CX1 and CX2 need to be connected externally in case of

fundamental mode oscillation (the fundamental frequency is represented by L, CL and

RS). Capacitance CP in Figure 31 represents the parallel package capacitance and should

not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal

manufacturer (see Table 25).

Fig 31. Oscillator modes and models: oscillation mode of operation and external crystal

model used for CX1/CX2 evaluation

Table 25.

Recommended values for CX1/CX2 in oscillation mode (crystal and external

components parameters) low frequency mode

Fundamental oscillation

frequency FOSC

Crystal load

capacitance CL

Maximum crystal

series resistance RS

External load

capacitors CX1, CX2

1 MHz - 5 MHz

10 pF

< 300



18 pF, 18 pF

20 pF

< 300



39 pF, 39 pF

30 pF

< 300



57 pF, 57 pF

5 MHz - 10 MHz

10 pF

< 300



18 pF, 18 pF

20 pF

< 200



39 pF, 39 pF

30 pF

< 100



57 pF, 57 pF

10 MHz - 15 MHz

10 pF

< 160



18 pF, 18 pF

20 pF

< 60



39 pF, 39 pF

15 MHz - 20 MHz

10 pF

< 80



18 pF, 18 pF

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