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LPC81XM датащи(PDF) 48 Page - NXP Semiconductors |
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LPC81XM датащи(HTML) 48 Page - NXP Semiconductors |
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48 / 67 page ![]() LPC81xM All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Objective data sheet Rev. 1.0 — 7 November 2012 48 of 67 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller [1] Tcy(clk) = <tbd>. [2] Tcy(clk) = 12 Tcy(PCLK). SPI slave (in SPI mode) Tcy(PCLK) PCLK cycle time <tbd> - - ns tDS data set-up time in SPI mode [2] <tbd> - - ns tDH data hold time in SPI mode 2.4 V V DD 3.6 V [2] <tbd> - - ns 2.0 V V DD < 2.4 V <tbd> ns 1.8 V V DD < 2.0 V <tbd> - - ns tv(Q) data output valid time in SPI mode [2] -- <tbd> ns th(Q) data output hold time in SPI mode [2] -- <tbd> ns Table 18. Dynamic characteristics of SPI pins Tamb = 40 C to 85 C; CL = <tbd>; 1.8 V <= VDD <= 3.6 V. Simulated parameters; values guaranteed by design. Symbol Parameter Conditions Min Typ Max Unit Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1. Fig 28. SPI master timing in SPI mode 6&.&32/ 026, 0,62 7F\FON WFON+ WFON/ W'6 W'+ WY4 '$7$ 9$/,' '$7$ 9$/,' WK4 6&.&32/ '$7$ 9$/,' '$7$ 9$/,' 026, 0,62 W'6 W'+ '$7$ 9$/,' '$7$ 9$/,' WK4 '$7$ 9$/,' '$7$ 9$/,' WY4 &3+$ &3+$ DDD |
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