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LPC81XM датащи(PDF) 38 Page - NXP Semiconductors |
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LPC81XM датащи(HTML) 38 Page - NXP Semiconductors |
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38 / 67 page ![]() LPC81xM All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Objective data sheet Rev. 1.0 — 7 November 2012 38 of 67 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 10.2 CoreMark data (1) WKT running. (1) WKT not running. Fig 17. Deep power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD X (X) X X X XX 001aac984 X X X X X X (X) X <tbd> External signal generator providing 1 MHz to 20 MHz signal drives the XTALIN input; when testing 1 MHz to 19 MHz the system PLL is OFF, SYSAHBCLKDIV = 1; when testing 20 MHz to 30 MHz the system PLL is configured so that SYSAHBCLKDIV = 1. Fig 18. CoreMark current consumption for power modes 0, 1, 2, and 3 X (X) X X X XX 001aac984 X X X X X X (X) X <tbd> |
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