LPC81XM datasheet(52/67 Pages) NXP

52 / 67 page

LPC81xM

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Objective data sheet

Rev. 1.0 — 7 November 2012

52 of 67

NXP Semiconductors

LPC81xM

32-bit ARM Cortex-M0+ microcontroller

[1]

Maximum values are derived from worst case simulation (VDD = 2.6 V; Tamb = 85 C; slow process models).

[2]

Settling time applies to switching between comparator channels<tbd>.

[1]

Measured <tbd> with a 2 kHz input signal and overdrive < 100

V.

[2]

All peripherals except comparator, temperature sensor, and IRC turned off.

13. Application information

13.1 XTAL input

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a

clock in slave mode, it is recommended that the input be coupled through a capacitor with

Ci = 100 pF. To limit the input voltage to the specified range, choose an additional

capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave

mode, a minimum of 200 mV(RMS) is needed.

Table 24.

Comparator voltage ladder reference static characteristics

VDD(3V3) = 3.3 V; Tamb = -40 C to + 85C.

Symbol

Parameter

Conditions

Min

Typ

Max[1]

Unit

EV(O)

output voltage error

Internal VDD(3V3) supply

decimal code = 00

[2]

<tbd>

decimal code = 08

<tbd>

decimal code = 16

<tbd>

decimal code = 24

<tbd>

decimal code = 30

<tbd>

decimal code = 31

<tbd>

EV(O)

output voltage error

External VDDCMP

supply

decimal code = 00

<tbd>

decimal code = 08

<tbd>

decimal code = 16

<tbd>

decimal code = 24

<tbd>

decimal code = 30

<tbd>

decimal code = 31

<tbd>

Fig 30. Slave mode operation of the on-chip oscillator

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