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S29GL01GS датащи(PDF) 102 Page - SPANSION |
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S29GL01GS датащи(HTML) 102 Page - SPANSION |
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102 / 104 page ![]() 102 GL-S MirrorBit® Family S29GL_128S_01GS_00_06 March 16, 2012 Da ta Sh e e t 15. Revision History Section Description Revision 01 (February 11, 2011) Initial release Revision 02 (March 21, 2011) Global Modified document from “Advance Information” to “Preliminary” OPN Added FBGA package offering for V1 & V2 Model Number Removed KGD information, which is documented in a separate Supplement Command Definitions Table Removed duplicated commands Changed the number of command cycles for a CFI Enter from 3 to 1 Physical Interface Updated 56-pin TSOP pinout figure Updated 64-ball FBGA pinout figure Other Resources Added additional application notes in “Links to Application Notes” Lock Register Table Changed the default value of bit 7 in the Lock register Revision 03 (July 8, 2011) Performance Summary Updated table: Typical Program and Erase Rates Secure Silicon Region ASO Corrected table: Secure Silicon Region DQ1: Write-to-Buffer Abort Corrected table: Data Polling Staus Embedded Algorithm Performance Table Updated table: Embedded Algorithm Characteristics Command State Transitions Corrected tables: changed Software Reset/ASO Exit Data value to from 00F0h to xF0h Corrected table: Erase Suspend Unlock State Command Transition Corrected table: Erase Suspend - DYB State Command Transition Corrected table: Program Unlock State Command Transition Corrected table: Lock Register State Command Transition Corrected table: Secure Silicon Sector Program State Command Transition Corrected table: Password Protection Command State Transition Corrected table: Non-Volatile Protection Command State Transition Corrected table: PPB Lock Bit Command State Transition Corrected table: Volatile Sector Protection Command State Transition Device ID and Common Flash Interface (ID-CFI) ASO Map Corrected table: Corrected CFI Primary Vendor-Specific Extended Query description for Word Address (SA) + 0045h DC Characteristics Updated VIL Max Updated Note Power-On Reset (POR) and Warm Reset Updated table: added row to bottom of table Power-On (Cold) Reset (POR) Updated text Updated figure: Power-Up Diagram Hardware (Warm) Reset Updated figure: Hardware Reset Asynchronous Write Operations Added figure: Back to Back (CE#VIL) Write Operation Timing Diagram Updated table: Erase/Program Operations Physical Diagram - LAA064 Added figure |
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