S29GL01GS datasheet(66/104 Pages) SPANSION

66 / 104 page

GL-S MirrorBit® Family

S29GL_128S_01GS_00_06 March 16, 2012

Da ta

Sh e e t

7.4

Ready/Busy# (RY/BY#)

RY/BY# is a dedicated, open drain output pin that indicates whether an Embedded Algorithm, Power-On

Reset (POR), or Hardware Reset is in progress or complete. The RY/BY# status is valid after the rising edge

of the final WE# pulse in a command sequence, when VCC is above VCC minimum during POR, or after the

falling edge of RESET#. Since RY/BY# is an open drain output, several RY/BY# pins can be tied together in

parallel with a pull up resistor to VIO.

If the output is Low (Busy), the device is actively erasing, programming, or resetting. (This includes

programming in the Erase Suspend mode). If the output is High (Ready), the device is ready to read data

(including during the Erase Suspend mode), or is in the standby mode.

Table 5.3, Data Polling Status on page 42 shows the outputs for RY/BY# in each operation.

If an Embedded algorithm has failed (Program / Erase failure as result of max pulses or Sector is locked),

RY/BY# will stay Low (busy) until status register bits 4 and 5 are cleared and the reset command is issued.

This includes Erase or Programming on a locked sector.

7.5

Hardware Reset

The RESET# input provides a hardware method of resetting the device to standby state. When RESET# is

driven Low for at least a period of tRP, the device immediately:

 terminates any operation in progress,

 exits any ASO,

 tristates all outputs,

 resets the Status Register,

 resets the EAC to standby state.

 CE# is ignored for the duration of the reset operation (t

RPH).

 To meet the Reset current specification (I

CC5) CE# must be held High.

To ensure data integrity any operation that was interrupted should be reinitiated once the device is ready to

accept another command sequence.

S29GL01GS датащи(PDF) 66 Page - SPANSION