S29GL01GS datasheet(69/104 Pages) SPANSION

69 / 104 page

March 16, 2012 S29GL_128S_01GS_00_06

GL-S MirrorBit® Family

Data

She e t

8.4.2

Random (Asynchronous) Read

When the host system interface selects the memory device by driving CE# Low, the device interface leaves

the Standby state. If WE# is High when CE# goes Low, a random read access is started. The data output

depends on the address map mode and the address provided at the time the read access is started.

The data appears on DQ15-DQ0 when CE# is Low, OE# is Low, WE# remains High, address remains stable,

and the asynchronous access times are satisfied. Address access time (tACC) is equal to the delay from

stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable CE# to valid

data at the outputs. In order for the read data to be driven on to the data outputs the OE# signal must be Low

at least the output enable time (tOE) before valid data is available.

At the completion of the random access time from CE# active (tCE), address stable (tACC), or OE# active

(tOE), whichever occurs latest, the data outputs will provide valid read data from the currently active address

map mode. If CE# remains Low and any of the A

MAX to A4 address signals change to a new value, a new

random read access begins. If CE# remains Low and OE# goes High the interface transitions to the Read

with Output Disable state. If CE# remains Low, OE# goes High, and WE# goes Low, the interface transitions

to the Write state. If CE# returns High, the interface goes to the Standby state. Back to Back accesses, in

which CE# remains Low between accesses, requires an address change to initiate the second access.

See Asynchronous Read Operations on page 80.

8.4.3

Page Read

After a Random Read access is completed, if CE# remains Low, OE# remains Low, the A

MAX to A4 address

signals remain stable, and any of the A3 to A0 address signals change, a new access within the same Page

begins. The Page Read completes much faster (tPACC) than a Random Read access.

8.5

Write

8.5.1

Asynchronous Write

When WE# goes Low after CE is Low, there is a transition from one of the read states to the Write state. If

WE# is Low before CE# goes Low, there is a transition from the Standby state directly to the Write state

without beginning a read access.

When CE# is Low, OE# is High, and WE# goes Low, a write data transfer begins. Note, OE# and WE# should

never be Low at the same time to ensure no data bus contention between the host system and memory.

When the asynchronous write cycle timing requirements are met the WE# can go High to capture the address

and data values in to EAC command memory.

Address is captured by the falling edge of WE# or CE#, whichever occurs later. Data is captured by the rising

edge of WE# or CE#, whichever occurs earlier.

When CE# is Low before WE# goes Low and stays Low after WE# goes High, the access is called a WE#

controlled Write. When WE# is High and CE# goes High, there is a transition to the Standby state. If CE#

remains Low and WE# goes High, there is a transition to the Read with Output Disable state.

When WE# is Low before CE# goes Low and remains Low after CE# goes High, the access is called a CE#

controlled Write. A CE# controlled Write transitions to the Standby state.

If WE# is Low before CE# goes Low, the write transfer is started by CE# going Low. If WE# is Low after CE#

goes High, the address and data are captured by the rising edge of CE#. These cases are referred to as CE#

controlled write state transitions.

Write followed by Read accesses, in which CE# remains Low between accesses, requires an address

change to initiate the following read access.

Back to Back accesses, in which CE# remains Low between accesses, requires an address change to initiate

the second access.

The EAC command memory array is not readable by the host system and has no ASO. The EAC examines

the address and data in each write transfer to determine if the write is part of a legal command sequence.

When a legal command sequence is complete the EAC will initiate the appropriate EA.

S29GL01GS датащи(PDF) 69 Page - SPANSION

S29GL01GS датащи(HTML) 69 Page - SPANSION

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL