SPC56EC74L7 datasheet(51/118 Pages) STMICROELECTRONICS

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SPC564Bxx - SPC56ECxx

Electrical Characteristics

Doc ID 17478 Rev 4

51/118

4.4

Recommended operating conditions

Table 10.

Recommended operating conditions (3.3 V)

Symbol

Parameter

Conditions

Value

Unit

Min

Max

VSS_HV

SR Digital ground on VSS_HV pins

—

VDD_HV_A

(1)

Voltage on VDD_HV_A pins with

respect to ground (VSS_HV)

—3.0

3.6

VDD_HV_B

(1)

Voltage on VDD_HV_B pins with

respect to ground (VSS_HV)

—3.0

3.6

VSS_LV

(2)

Voltage on VSS_LV (low

voltage digital supply) pins with

respect to ground (VSS_HV)

—VSS_HV − 0.1

VSS_HV +0.1

VRC_CTRL

(3)

Base control voltage for

external BCP68 NPN device

Relative to VDD_LV

0VDD_LV +1

VSS_ADC

Voltage on VSS_HV_ADC0,

VSS_HV_ADC1 (ADC

reference) pin with respect to

ground (VSS_HV)

—VSS_HV − 0.1

VSS_HV +0.1

VDD_HV_ADC0

(4)

Voltage on VDD_HV_ADC0

with respect to ground

(VSS_HV)

—3.0(5)

3.6

Relative to

VDD_HV_A

(6)

VDD_HV_A − 0.1

VDD_HV_A + 0.1

VDD_HV_ADC1

(7)

Voltage on VDD_HV_ADC1

with respect to ground

(VSS_HV)

—3.0

3.6

Relative to

VDD_HV_A

(6)

VDD_HV_A − 0.1

VDD_HV_A +0.1

VIN

Voltage on any GPIO pin with

respect to ground (VSS_HV)

—VSS_HV − 0.1

—

Relative to

VDD_HV_A/HV_B

—

VDD_HV_A/HV_B

+0.1

IINJPAD

Injected input current on any

pin during overload condition

—

−55

IINJSUM

Absolute sum of all injected

input currents during overload

condition

—

−50

TVDD

VDD_HV_A slope to ensure

correct power up(8)

——

0.5

V/µs

—

0.5

—

V/min

Ambient temperature under

bias

fCPU up to

120 MHz

+ 2%

–40

125

°C

Junction temperature under

bias

—

−40

150

100 nF EMI capacitance and 10 µF bulk capacitance need to be provided between each VDD/VSS_HV pair.

100 nF EMI capacitance and 10 µF bulk capacitance need to be provided between each of the four VDD_LV/VSS_LV supply

pairs. For details refer to the Power Management chapter of the SPC564Bxx and SPC56ECxx Reference Manual.

This voltage is internally generated by the device and no external voltage should be supplied.

100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.

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