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SPC56EC74L7 датащи(PDF) 93 Page - STMicroelectronics

номер детали SPC56EC74L7
подробное описание детали  32-bit MCU family built on the Power Architecture® for automotive body electronics applications
PDF  118 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
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SPC56EC74L7 датащи(HTML) 93 Page - STMicroelectronics

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SPC564Bxx - SPC56ECxx
Electrical Characteristics
Doc ID 17478 Rev 4
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exceed four times the TX_CLK frequency in 2:1 mode and two times the TX_CLK frequency
in 1:1 mode.
The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from
either the rising or falling edge of TX_CLK, and the timing is the same in either case. This
options allows the use of non-compliant MII PHYs.
Refer to the Fast Ethernet Controller (FEC) chapter of the SPC564B74 and SPC56EC74
Reference Manual for details of this option and how to enable it.
Figure 22. MII transmit signal timing diagram
4.18.3
MII Async Inputs Signal Timing (CRS and COL)
Figure 23. MII async inputs timing diagram
Table 46.
MII transmit signal timing(1)
Spec
Characteristic
Min
Max
Unit
M5
TX_CLK to TXD[3:0],
TX_EN, TX_ER invalid
5—
ns
M6
TX_CLK to TXD[3:0],
TX_EN, TX_ER valid
—25
ns
M7
TX_CLK pulse width high
35%
65%
TX_CLK period
M8
TX_CLK pulse width low
35%
65%
TX_CLK period
1.
Output pads configured with SRE = 0b11.
M6
TX_CLK (input)
TXD[3:0] (outputs)
TX_EN
TX_ER
M5
M7
M8
Table 47.
MII Async Inputs Signal Timing(1)
Spec
Characteristic
Min
Max
Unit
M9
CRS, COL minimum pulse width
1.5
—
TX_CLK period
1.
Output pads configured with SRE = 0b11.
CRS, COL
M9



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