| поискавой системы для электроныых деталей |
|
SPC56EC74L7 датащи(PDF) 88 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
SPC56EC74L7 датащи(HTML) 88 Page - STMicroelectronics |
|
88 / 118 page ![]() Electrical Characteristics SPC564Bxx - SPC56ECxx 88/118 Doc ID 17478 Rev 4 RSW1 CC D Internal resistance of analog source —— — 3 k Ω RSW2 CC D Internal resistance of analog source —— — 2 k Ω RAD CC D Internal resistance of analog source —— — 2 k Ω IINJ SR — Input current Injection Current injection on one ADC_0 input, different from the converted one VDD = 3.3 V ± 10% −5— 5 mA VDD = 5.0 V ± 10% −5— 5 | INL | CC T Absolute value for integral non-linearity No overload — 0.5 1.5 LSB | DNL | CC T Absolute differential non-linearity No overload — 0.5 1.0 LSB | OFS | CC T Absolute offset error — — 0.5 — LSB | GNE | CC T Absolute gain error — — 0.6 — LSB TUEP CC P Total unadjusted error(7) for precise channels, input only pins Without current injection −20.6 2 LSB T With current injection −33 TUEX CC T Total unadjusted error(7) for extended channel Without current injection −31 3 LSB T With current injection −44 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified. 2. Analog and digital VSS_HV must be common (to be tied together externally). 3. VAINx may exceed VSS_ADC0 and VDD_ADC0 limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0x3FF. 4. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tADC0_S. After the end of the sample time tADC0_S, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tADC0_S depend on programming. 5. Conversion time = Bit evaluation time + Sampling time + 1 Clock cycle delay. 6. Refer to ADC conversion table for detailed calculations. 7. Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a combination of Offset, Gain and Integral Linearity errors. Table 43. ADC conversion characteristics (10-bit ADC_0) (continued) Symbol C Parameter Conditions(1) Value Unit Min Typ Max |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |