MPC5645S datasheet(11/146 Pages) FREESCALE

11 / 146 page

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Multiple processors can assert interrupt requests to each other through software setable interrupt requests. These same software

setable interrupt requests also can be used to break the work involved in servicing an interrupt request into a high priority portion

and a low priority portion. The high priority portion is initiated by a peripheral interrupt request, but then the ISR asserts a

software setable interrupt request to finish the servicing in a lower priority ISR. Therefore these software setable interrupt

requests can be used instead of the peripheral ISR scheduling a task through the RTOS. The INTC provides the following

features:

•

Unique 9-bit vector for each of the possible 128 separate interrupt sources

•

Eight software triggerable interrupt sources

•

16 priority levels with fixed hardware arbitration within priority levels for each interrupt source

•

Ability to modify the ISR or task priority

— Modifying the priority can be used to implement the Priority Ceiling Protocol for accessing shared resources

•

External non maskable interrupt directly accessing the main CPU critical interrupt mechanism

•

32 external interrupts

1.4.6

QuadSPI serial flash memory controller

The QuadSPI module enables use of external serial flash memories supporting single, dual, and quad modes of operation. It

features the following:

•

Maximum serial clock frequency 80 MHz

•

Memory mapped read access for AHB crossbar switch masters

•

Automatic serial flash read command generation by CPU, eDMA, DCU, or DCULite read access on AHB bus

•

Supports single, dual, and quad serial flash read commands

•

Simultaneous mode:

— Supports concurrent read of two external serial flashes

— The quad data streams from the two flashes can be recombined in the QuadSPI to achieve up to 80 MB/s read

bandwidth with 80 MHz serial flash

•16

64-bit buffer with speculative fetch and buffer flush mechanisms to maximize read bandwidth of serial flash

•

DMA support

•

All Serial Flash program, erase, read, and configuration commands available via IP bus interface

1.4.7

System Integration Unit Lite (SIUL)

The SIUL controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal

peripheral multiplexing, and the system reset operation.

The GPIO features the following:

•

Up to four levels of internal pin multiplexing, allowing exceptional flexibility in the allocation of device functions for

each package

•

Centralized general purpose input output (GPIO) control

•

All GPIO pins can be independently configured to support pull-up, pull down, or no pull

•

Reading and writing to GPIO supported both as individual pins and 16-bit wide ports

•

All peripheral pins can be alternatively configured as both general purpose input or output pins except ADC channels

which support alternative configuration as general purpose inputs

•

Direct readback of the pin value supported on all digital output pins through the SIU

•

Configurable digital input filter that can be applied to up to 24 general purpose input pins for noise elimination on

external interrupts

•

modification until next reset

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