MPC5645S datasheet(35/146 Pages) FREESCALE

35 / 146 page

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Figure 5. VIU2, DCU3, and DCULite pin sharing

VIU input data selection is done based on select bit (bit 0) of Miscellaneous control register (0xC3FE0340).

•

VIU pix data: VIU[9:0]

•

Select bit 1’b0: PDI[7:0],HSYNC,VSYNC

•

Select bit 1’b1: PDI[17:8]

2.4.7

SGM muxing

The SGM shares pins between the PWM output signals and the I2S bus signals as shown in the Table . “Port pin summary

table. When the PWM function is enabled in the SGM (SGMCTL[PWME]) the PWM (PWMO, PWMOA) signals are available.

When the PWM function is disabled the I2S bus signals (I2S_DO, I2S_SCK) are available.

2.4.8

RSDS special function muxing

Ports PA[0:15], PG[0:7], PG[11] and PM[2] have the RSDS signalling option as a special function. The SIUL allocates pad

control registers to these functions (PCR[270:282]), but because these pads share a common pin with the normal GPIO pins

they do not operate in the same way as the normal GPIO ports. PG[11] in particular has a special configuration separate from

the other pads.

The special-function pads are output-only, and the associated PCR[OBE] bit is controlled by the TCON_CTRL1 register

(TCON_BYPASS and RSDS_MODE bits). However, the alternate function selection is taken from the associated normal GPIO

pad. This allows selection of the DCU3 function as the alternate function of the pad and then the TCON module to select if the

output style is TCON/RSDS or digital RGB format.

Therefore, when the TCON bypass is active (bypass disabled with or without RSDS active), it is important not to configure the

normal GPIO ports for output operation with a non-DCU3 alternate function on ports PA[0:15] and PG[0:7].

For PG[11], the PCR[282] OBE bit is fully controlled by the TCON module and will become an output whenever the DCU3

alternate option is selected. Therefore, only select the DCU3 function on this pin when ready to configure it as a clock for a TFT

panel.

VIU2

DCU3

DCULite

PDI

VIU[9:0]

PDI_PCLK

VSYNC

HSYNC

DATA[17:0]

VIU_PCLK

XBAR

Direct feed of PDI interface

to DCU3 or DCULite

RGB565

RGB888

8-bit mono

YUV422

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