MPC5645S datasheet(62/146 Pages) FREESCALE

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Qorivva MPC5645S Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

VDDR

SR P Voltage on VDDR pin (regulator supply) with

respect to ground (VSSR)

—+3.0

+3.6

D2.4

Relative to VDD VDD–0.1

VDD+0.1

VSSR

SR D Voltage on VSSR (regulator ground) pin with

respect to VSS

—VSS–0.1

VSS+0.1

D2.5

VDD12

3,4

CC P Voltage on VDD12 pin with respect to ground

(VSS12)

—1.08

1.4

D2.6

VSS12

CC D Voltage on VSS12 pin with respect to VSS

—VSS–0.1

VSS+0.1

D2.7

VDD

5,6,7

SR P Voltage on VDD pins (VDDE_A, VDDE_B,

VDD_DR, VDDM) with respect to ground (VSS)

—VDDmin

VDDmax

VD2.8

VSS

SR D I/O supply ground

—

D2.9

VDDE_A

SR P Voltage on VDDE_A (I/O supply) pin with

respect to ground (VSSE_A)

—+3.0

+3.6

D2.10

VDDE_B SR P Voltage on VDDE_B (I/O supply) pin with

respect to ground (VSSE_B)

—+3.0

+3.6

D2.11

VDDM

SR P Voltage on VDDM (stepper motor supply) pin

with respect to ground (VSSM)

—+3.0

+3.6

D2.12

VDD_DR

P Voltage on VDDDDR with respect to VSS

—

+1.62

+3.6

D2.13

VSS_DR

D Voltage on VSSRSDS with respect to VSS

—

+1.62

+3.6

D2.14

VRSDS

P Voltage on VDDDDR with respect to VSS

—+3.0

+3.6

D2.15

TVDD

SR D VDD slope to ensure correct power up

——

V/ms

D2.16

SR P Ambient temperature under bias

—

-40

+105

°C

D2.17

SR D Junction temperature under bias

-40

+140

D2.18

1 100 nF capacitance needs to be provided between V

DDA/VSSA pair.

2 10

F capacitance must be connected between V

DDR and VSS12 because of a sharp surge due to external ballast.

3 V

DD12 cannot be used to drive any external component.

4 Each V

DD12/VSS12 supply pair should have a 10 F capacitor. Absolute combined maximum capacitance is 40 F. Preferably,

all the VDD12 supply pads should be shorted and then connected to a 4

10 F capacitance. This is to ensure the ESR of

external capacitance does not exceed 0.2

. A 100 nF capacitor must be placed close to the pin.

5 V

DD refers collectively to I/O voltage supplies, i.e., VDDE_A, VDDE_B, VDD_DR, and VDDM.

6 100 nF capacitance needs to be provided between each V

DD/VSS pair. VDDmin value for is 3 V for VDDE_A & VDDM as well

as for VDDE_B, while it is 1.62 V for VDD_DR. VDD max value is 3.6 V for VDDE_A & VDDM as well as for VDDE_B &

VDD_DR.

7 Full electrical specification cannot be guaranteed when voltage drops below 3.0V. In particular, ADC electrical characteristics

and I/O’s DC electrical specification may not be guaranteed.

When voltage drops below VLVDHVL device is reset.

8 V

SS refers collectively to I/O voltage supply grounds, i.e., VSSE_A, VSS, and VSSM unless otherwise noted.

9 V

DDE_A should not be less than VDDA.

10 Guaranteed by device validation.

Table 11. Recommended operating conditions (3.3 V) (continued)

Symbol

Parameter

Conditions

Value

Unit

SpecID

Min

Max

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